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SN74LVC2G17

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2-ch, 1.65-V to 5.5-V buffers with Schmitt-Trigger inputs

Data sheet
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2-ch, 1.65-V to 5.5-V buffers with Schmitt-Trigger inputs

SN74LVC2G17

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Data sheet Order now

Product details

Parameters

Technology Family LVC Supply voltage (Min) (V) 1.65 Supply voltage (Max) (V) 5.5 Number of channels (#) 2 IOL (Max) (mA) 32 ICC (Max) (uA) 10 IOH (Max) (mA) -32 Input type Schmitt-Trigger Output type Push-Pull Features Balanced outputs, Very high speed (tpd 5-10ns), Partial power down (Ioff), Over-voltage tolerant inputs Rating Catalog open-in-new Find other Non-Inverting buffer/driver

Package | Pins | Size

DSBGA (YZP) 6 2 mm² .927 x 1.427 SOT-23 (DBV) 6 5 mm² 2.9 x 1.6 SOT-SC70 (DCK) 6 4 mm² 2 x 2.1 USON (DRY) 6 1 mm² 1.5 x 1 X2SON (DSF) 6 1 mm² 1 x 1 open-in-new Find other Non-Inverting buffer/driver

Features

  • Schmitt-Trigger inputs provide hysteresis
  • Available in the Texas Instruments NanoFree™ Package
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 5.4 ns at 3.3 V
  • Low Power Consumption, 10-µA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Typical VOLP (Output Ground Bounce)
    < 0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    > 2 V at VCC = 3.3 V, TA = 25°C
  • Ioff Supports Live Insertion, Partial-Power-Down Mode
    Operation and Back-Drive Protection
  • Latch-Up Performance Exceeds 100 mA Per JESD 78,
    Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model
    • 1000-V Charged-Device Model
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Description

This dual Schmitt-Trigger buffer is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC2G17 device contains two buffers and performs the Boolean function Y = A. The device functions as two independent buffers, but because of Schmitt action, it may have different input threshold levels for positive-going (VT+) and negative-going (VT–) signals.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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Technical documentation

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Type Title Date
* Data sheet SN74LVC2G17 Dual Schmitt-Trigger Buffer datasheet (Rev. N) Jan. 25, 2015
Selection guide Little Logic Guide 2018 (Rev. G) Jul. 06, 2018
Selection guide Logic Guide (Rev. AB) Jun. 12, 2017
Application note How to Select Little Logic (Rev. A) Jul. 26, 2016
Application note Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
Application note Understanding Schmitt Triggers Sep. 21, 2011
User guide LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
More literature Design Summary for WCSP Little Logic (Rev. B) Nov. 04, 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
Application note Selecting the Right Level Translation Solution (Rev. A) Jun. 22, 2004
User guide Signal Switch Data Book (Rev. A) Nov. 14, 2003
Application note Use of the CMOS Unbuffered Inverter in Oscillator Circuits Nov. 06, 2003
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
User guide LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) Dec. 18, 2002
Application note Texas Instruments Little Logic Application Report Nov. 01, 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards Jun. 13, 2002
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) May 22, 2002
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices May 10, 2002
More literature STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS Mar. 27, 2002
More literature Military Low Voltage Solutions Apr. 04, 2001
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices Dec. 01, 1997
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) Aug. 01, 1997
Application note CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application note LVC Characterization Information Dec. 01, 1996
Application note Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application note Live Insertion Oct. 01, 1996
User guide Low-Voltage Logic (LVC) Designer's Guide Sep. 01, 1996
Application note Understanding Advanced Bus-Interface Products Design Guide May 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
document-generic User guide
10
Description
Flexible EVM designed to support any device that has a DCK, DCT, DCU, DRL, or DBV package in a 5 to 8 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices
View details

Design tools & simulation

SIMULATION MODEL Download
SCEM253D.ZIP (43 KB) - IBIS Model
SIMULATION MODEL Download
SCEM615.ZIP (7 KB) - PSpice Model

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TIDM-SOLAR-DCDC — This design is a digitally-controlled, solar DC/DC converter with maximum power point tracking (MPPT), for use in central or string solar inverters. It is a companion to the TI Design TIDM-SOLAR-ONEPHINV, a grid-tied, single phase, DC/AC inverter. Together, the TIDM-SOLAR-DCDC and the (...)
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CAD/CAE symbols

Package Pins Download
DSBGA (YZP) 6 View options
SC70 (DCK) 6 View options
SON (DRY) 6 View options
SON (DSF) 6 View options
SOT-23 (DBV) 6 View options

Ordering & quality

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  • Ongoing reliability monitoring

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