Product details

Configuration 1:1 SPST Number of channels (#) 2 Power supply voltage - single (V) 1.8, 2.5, 3.3, 5 Protocols Analog Ron (Typ) (Ohms) 6 CON (Typ) (pF) 14 ON-state leakage current (Max) (µA) 1 Bandwidth (MHz) 300 Operating temperature range (C) -40 to 85 Input/output continuous current (Max) (mA) 50 Rating Catalog Supply current (Typ) (uA) 1
Configuration 1:1 SPST Number of channels (#) 2 Power supply voltage - single (V) 1.8, 2.5, 3.3, 5 Protocols Analog Ron (Typ) (Ohms) 6 CON (Typ) (pF) 14 ON-state leakage current (Max) (µA) 1 Bandwidth (MHz) 300 Operating temperature range (C) -40 to 85 Input/output continuous current (Max) (mA) 50 Rating Catalog Supply current (Typ) (uA) 1
DSBGA (YZP) 8 3 mm² .928 x 1.928 SSOP (DCT) 8 8 mm² 3 x 2.8 SSOP (DCT) 8 8 mm² 2.95 x 2.80 VSSOP (DCU) 8 6 mm² 2 x 3.1
  • Available in the Texas Instruments
    NanoFree™ Package
  • 1.65-V to 5.5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 0.8 ns at 3.3 V
  • High On-Off Output Voltage Ratio
  • High Degree of Linearity
  • High Speed, Typically 0.5 ns
    (VCC = 3 V, CL = 50 pF)
  • Rail-to-Rail Input/Output
  • Low ON-State Resistance, Typically ≉6 Ω
    (VCC = 4.5 V)
  • Latch-Up Performance Exceeds 100 mA Per
    JESD 78, Class II
  • Available in the Texas Instruments
    NanoFree™ Package
  • 1.65-V to 5.5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 0.8 ns at 3.3 V
  • High On-Off Output Voltage Ratio
  • High Degree of Linearity
  • High Speed, Typically 0.5 ns
    (VCC = 3 V, CL = 50 pF)
  • Rail-to-Rail Input/Output
  • Low ON-State Resistance, Typically ≉6 Ω
    (VCC = 4.5 V)
  • Latch-Up Performance Exceeds 100 mA Per
    JESD 78, Class II

This dual bilateral analog switch is designed for
1.65-V to 5.5-V VCC operation.

The SN74LVC2G66 device can handle both analog and digital signals. The SN74LVC2G66 device permits signals with amplitudes of up to 5.5 V (peak) to be transmitted in either direction.

NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.

Each switch section has its own enable-input control (C). A high-level voltage applied to C turns on the associated switch section.

Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for analog-to-digital and digital-to-analog conversion systems.

This dual bilateral analog switch is designed for
1.65-V to 5.5-V VCC operation.

The SN74LVC2G66 device can handle both analog and digital signals. The SN74LVC2G66 device permits signals with amplitudes of up to 5.5 V (peak) to be transmitted in either direction.

NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.

Each switch section has its own enable-input control (C). A high-level voltage applied to C turns on the associated switch section.

Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for analog-to-digital and digital-to-analog conversion systems.

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Technical documentation

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Type Title Date
* Data sheet SN74LVC2G66 Dual Bilateral Analog Switch datasheet (Rev. N) PDF | HTML 20 Aug 2018
Application note Selecting the Correct Texas Instruments Signal Switch (Rev. E) PDF | HTML 02 Jun 2022
Application note Multiplexers and Signal Switches Glossary (Rev. B) PDF | HTML 01 Dec 2021
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Little Logic Guide 2018 (Rev. G) 06 Jul 2018
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note How to Select Little Logic (Rev. A) 26 Jul 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
More literature Design Summary for WCSP Little Logic (Rev. B) 04 Nov 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
Application note Use of the CMOS Unbuffered Inverter in Oscillator Circuits 06 Nov 2003
More literature Logic Cross-Reference (Rev. A) 07 Oct 2003
More literature I2C and Serial Bus Devices Application Clip 10 Jul 2003
User guide LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) 18 Dec 2002
Application note Texas Instruments Little Logic Application Report 01 Nov 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards 13 Jun 2002
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 22 May 2002
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 10 May 2002
More literature STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS 27 Mar 2002
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 01 Dec 1997
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 Aug 1997
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note LVC Characterization Information 01 Dec 1996
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996
Application note Live Insertion 01 Oct 1996
Design guide Low-Voltage Logic (LVC) Designer's Guide 01 Sep 1996
Application note Understanding Advanced Bus-Interface Products Design Guide 01 May 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

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The (...)

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Interface adapter

LEADED-ADAPTER1 — Surface mount to DIP header adapter for quick testing of TI's 5, 8, 10, 16 & 24-pin leaded packages

The EVM-LEADED1 board allows for quick testing and bread boarding of TI's common leaded packages.  The board has footprints to convert TI's D, DBQ, DCT,DCU, DDF, DGS, DGV, and PW surface mount packages to 100mil DIP headers.     

Not available on TI.com
Interface adapter

LEADLESS-ADAPTER1 — Surface mount to DIP header adapter for testing of TI's 6,8,10,12,14,16, & 20-pin leadless packages

The EVM-LEADLESS1 board allows for quick testing and bread boarding of TI's common leadless packages.  The board has footprints to convert TI's DRC, DTP, DQE, RBW, RGY, RSE, RSV, RSW RTE, RTJ, RUK , RUC, RUG, RUM,RUT and YZP surface mount packages to 100mil DIP headers.
Not available on TI.com
Simulation model

HSPICE Model for SN74LVC2G66

SCEJ257.ZIP (87 KB) - HSpice Model
Simulation model

SN74LVC2G66 IBIS Model

SCEM446.ZIP (34 KB) - IBIS Model
Reference designs

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Reference designs

TIDA-01572 — Stereo Evaluation Module Reference Design of the Digital Input, Class-D, IV Sense Audio Amplifier

This reference design provides a high-performance stereo audio subsystem for use in PC applications. It operates off a single supply, ranging from 4.5 V to 16 V, and features the TAS2770, a digital-input Class-D audio amplifier that provides excellent noise and distortion performance and is (...)
Package Pins Download
DSBGA (YZP) 8 View options
SM8 (DCT) 8 View options
VSSOP (DCU) 8 View options

Ordering & quality

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