SN74SSTV16859

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200-MHz, 13-bit to 26-bit registered buffer with SSTL_2 inputs and outputs

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Data sheet

document-pdfAcrobat SN74SSTV16859 datasheet (Rev. D)

SN74SSTV16859

ACTIVE

Data sheet

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Product details

Number of outputs

26

Core supply voltage (V)

2.5

Output supply voltage (V)

2.5

Operating temperature range (°C)

0 to 70

Rating

Military

Output type

SSTL-18

Input type

SSTL-18

Number of outputs

26

Core supply voltage (V)

2.5

Output supply voltage (V)

2.5

Operating temperature range (°C)

0 to 70

Rating

Military

Output type

SSTL-18

Input type

SSTL-18

TSSOP (DGG)

64

137.7 mm² (17 mm × 8.1 mm)

VQFNP (RGQ)

56

64 mm² (8 mm × 8 mm)

Member of the Texas Instruments Widebus™ Family
1-to-2 Outputs to Support Stacked DDR DIMMs
Supports SSTL_2 Data Inputs
Outputs Meet SSTL_2 Class II Specifications
Differential Clock (CLK and CLK\) Inputs
Supports LVCMOS Switching Levels on the RESET\ Input
RESET\ Input Disables Differential Input Receivers, Resets All Registers, and Forces All Outputs Low
Pinout Optimizes DIMM PCB Layout
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)

Widebus is a trademark of Texas Instruments.

Member of the Texas Instruments Widebus™ Family
1-to-2 Outputs to Support Stacked DDR DIMMs
Supports SSTL_2 Data Inputs
Outputs Meet SSTL_2 Class II Specifications
Differential Clock (CLK and CLK\) Inputs
Supports LVCMOS Switching Levels on the RESET\ Input
RESET\ Input Disables Differential Input Receivers, Resets All Registers, and Forces All Outputs Low
Pinout Optimizes DIMM PCB Layout
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)

Widebus is a trademark of Texas Instruments.

This 13-bit to 26-bit registered buffer is designed for 2.3-V to 2.7-V V_CC operation.

All inputs are SSTL_2, except the LVCMOS reset (RESET)\ input. All outputs are SSTL_2, Class II compatible.

The SN74SSTV16859 operates from a differential clock (CLK and CLK\). Data are registered at the crossing of CLK going high and CLK\ going low.

The device supports low-power standby operation. When RESET\ is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (V_REF) inputs are allowed. In addition, when RESET\ is low, all registers are reset and all outputs are forced low. The LVCMOS RESET\ input always must be held at a valid logic high or low level.

To ensure defined outputs from the register before a stable clock has been supplied, RESET\ must be held in the low state during power up.

This 13-bit to 26-bit registered buffer is designed for 2.3-V to 2.7-V V_CC operation.

All inputs are SSTL_2, except the LVCMOS reset (RESET)\ input. All outputs are SSTL_2, Class II compatible.

The SN74SSTV16859 operates from a differential clock (CLK and CLK\). Data are registered at the crossing of CLK going high and CLK\ going low.

The device supports low-power standby operation. When RESET\ is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (V_REF) inputs are allowed. In addition, when RESET\ is low, all registers are reset and all outputs are forced low. The LVCMOS RESET\ input always must be held at a valid logic high or low level.

To ensure defined outputs from the register before a stable clock has been supplied, RESET\ must be held in the low state during power up.

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Technical documentation

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Top documentation	Type	Title	Format options	Date
*	Data sheet	SN74SSTV16859 datasheet (Rev. D)		Aug 3, 2004
	Application note	Low-Power Support Using Texas Instruments SN74SSTV16857 and SN74SSTV16859		Feb 9, 2001