SN74SSTV16859 13-Bit to 26-Bit Registered Buffer with SSTL_2 Inputs and Outputs | TI.com

SN74SSTV16859
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13-Bit to 26-Bit Registered Buffer with SSTL_2 Inputs and Outputs

13-Bit to 26-Bit Registered Buffer with SSTL_2 Inputs and Outputs - SN74SSTV16859
Datasheet
 

Description

This 13-bit to 26-bit registered buffer is designed for 2.3-V to 2.7-V VCC operation.

All inputs are SSTL_2, except the LVCMOS reset (RESET)\ input. All outputs are SSTL_2, Class II compatible.

The SN74SSTV16859 operates from a differential clock (CLK and CLK\). Data are registered at the crossing of CLK going high and CLK\ going low.

The device supports low-power standby operation. When RESET\ is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET\ is low, all registers are reset and all outputs are forced low. The LVCMOS RESET\ input always must be held at a valid logic high or low level.

To ensure defined outputs from the register before a stable clock has been supplied, RESET\ must be held in the low state during power up.

Features

  • Member of the Texas Instruments Widebus™ Family
  • 1-to-2 Outputs to Support Stacked DDR DIMMs
  • Supports SSTL_2 Data Inputs
  • Outputs Meet SSTL_2 Class II Specifications
  • Differential Clock (CLK and CLK\) Inputs
  • Supports LVCMOS Switching Levels on the RESET\ Input
  • RESET\ Input Disables Differential Input Receivers, Resets All Registers, and Forces All Outputs Low
  • Pinout Optimizes DIMM PCB Layout
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)

Widebus is a trademark of Texas Instruments.

Parametrics

Compare all products in Clock buffers Email Download to Excel
Part number Order Function Output frequency (Max) (MHz) Number of outputs VCC core (V) Features Operating temperature range (C) Rating Package Group Package size: mm2:W x L (PKG)
SN74SSTV16859 Order now Memory interface     200     26     2.5     DDR2 register     0 to 70     Catalog     TSSOP | 64
VQFN | 56    
64TSSOP: 138 mm2: 8.1 x 17 (TSSOP | 64)
56VQFN: 64 mm2: 8 x 8 (VQFN | 56)