Product details

Number of channels (#) 4 Power switch MOSFET Peak output current (A) 0.5 Input VCC (Min) (V) 4.75 Input VCC (Max) (V) 7 Features Low Quiescent Current Operating temperature range (C) 0 to 70 Rise time (ns) 20 Fall time (ns) 20 Prop delay (ns) 60 Input threshold TTL Channel input logic Inverting Input negative voltage (V) 0 Rating Catalog
Number of channels (#) 4 Power switch MOSFET Peak output current (A) 0.5 Input VCC (Min) (V) 4.75 Input VCC (Max) (V) 7 Features Low Quiescent Current Operating temperature range (C) 0 to 70 Rise time (ns) 20 Fall time (ns) 20 Prop delay (ns) 60 Input threshold TTL Channel input logic Inverting Input negative voltage (V) 0 Rating Catalog
PDIP (N) 16 181 mm² 19.3 x 9.4 SOIC (D) 16 59 mm² 9.9 x 6
  • Quadruple Circuits Capable of Driving High-Capacitance Loads at High Speeds
  • Output Supply Voltage Range From 5 V to 24 V
  • Low Standby Power Dissipation
  • VCC3 Supply Maximizes Output Source Voltage
  • Quadruple Circuits Capable of Driving High-Capacitance Loads at High Speeds
  • Output Supply Voltage Range From 5 V to 24 V
  • Low Standby Power Dissipation
  • VCC3 Supply Maximizes Output Source Voltage

The SN75374 is a quadruple NAND interface circuit designed to drive power MOSFETs from TTL inputs. It provides the high current and voltage necessary to drive large capacitive loads at high speeds.

The outputs can be switched very close to the VCC2 supply rail when VCC3 is about 3 V higher than VCC2. VCC3 can also be tied directly to VCC2 when the source voltage requirements are lower.

The SN75374 is a quadruple NAND interface circuit designed to drive power MOSFETs from TTL inputs. It provides the high current and voltage necessary to drive large capacitive loads at high speeds.

The outputs can be switched very close to the VCC2 supply rail when VCC3 is about 3 V higher than VCC2. VCC3 can also be tied directly to VCC2 when the source voltage requirements are lower.

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Type Title Date
* Data sheet SN75374 datasheet (Rev. A) 05 Nov 2004
Application note External Gate Resistor Selection Guide (Rev. A) 28 Feb 2020
Application note Understanding Peak IOH and IOL Currents (Rev. A) 28 Feb 2020
Technical article How to achieve higher system robustness in DC drives, part 3: minimum input pulse 19 Sep 2018
Technical article How to achieve higher system robustness in DC drives, part 2: interlock and deadtime 30 May 2018
Technical article Boosting efficiency for your solar inverter designs 24 May 2018
Technical article How to achieve higher system robustness in DC drives, part 1: negative voltage 17 Apr 2018

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PDIP (N) 16 View options
SOIC (D) 16 View options

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