The SN65C1406 and SN75C1406 are low-power BiMOS devices containing three independent drivers and receivers that are used to interface data terminal equipment (DTE) with data circuit-terminating equipment (DCE). These devices are designed to conform to TIA/EIA-232-F. The drivers and receivers of the SN65C1406 and SN75C1406 are similar to those of the SN75C188 quadruple driver and SN75C189A quadruple receiver, respectively. The drivers have a controlled output slew rate that is limited to a maximum of 30 V/us, and the receivers have filters that reject input noise pulses shorter than 1 us. Both these features eliminate the need for external components.
The SN65C1406 and SN75C1406 are designed using low-power techniques in a BiMOS technology. In most applications, the receivers contained in these devices interface to single inputs of peripheral devices such as ACEs, UARTs, or microprocessors. By using sampling, such peripheral devices are usually insensitive to the transition times of the input signals. If this is not the case, or for other uses, it is recommended that the SN65C1406 and SN75C1406 receiver outputs be buffered by single Schmitt input gates or single gates of the HCMOS, ALS, or 74F logic families.
The SN65C1406 is characterized for operation from \x9640°C to 85°C. The SN75C1406 is characterized for operation from 0°C to 70°C.
|Part number||Order||Drivers per package||Receivers per package||Logic voltage (Min) (V)||Data rate (Max) (kbps)||Main supply voltage (Nom) (V)||ESD HBM (kV)||Rating||Operating temperature range (C)||Package Group|
||3||3||5||120||5||2||Catalog||0 to 70||
PDIP | 16
SOIC | 16
SOIC | 16
SO | 16
|SN75C1154||Samples not available||4||4||5||95||5||0||Catalog||0 to 70||
PDIP | 20
SOIC | 20