Top

Product details

Parameters

Number of channels (#) 2 FIFOs (bytes) 16 Rx FIFO trigger levels (#) 4 Tx FIFO trigger levels (#) Programmable FIFO trigger levels No CPU interface X86 Baud rate (max) at Vcc = 1.8 V & with 16X sampling (Mbps) 0.625 Baud rate (max) at Vcc = 2.5 V & with 16X sampling (Mbps) 1 Baud rate (max) at Vcc = 3.3 V & with 16X sampling (Mbps) 1.25 Baud rate (max) at Vcc = 5.0 V & with 16X sampling (Mbps) 1.5 Operating voltage (V) 1.8, 2.5, 3.3, 5 Auto RTS/CTS Yes Rating Catalog Operating temperature range (C) -40 to 85, 0 to 70 open-in-new Find other UARTs

Package | Pins | Size

PLCC (FN) 44 307 mm² 17.53 x 17.53 open-in-new Find other UARTs

Features

  • Programmable Auto-RTS and Auto-CTS
  • In Auto-CTS Mode, CTS Controls the Transmitter
  • In Auto-RTS Mode, RCV FIFO Contents, and Threshold Control RTS
  • Serial and Modem Control Outputs Drive a RJ11 Cable Directly When Equipment is on the Same Power Drop
  • Capable of Running With All Existing TL16C450 Software
  • After Reset, All Registers Are Identical to the TL16C450 Register Set
  • Up to 24-MHz Clock Rate for up to 1.5-Mbaud Operation With VCC = 5 V
  • Up to 20-MHz Clock Rate for up to 1.25-Mbaud Operation With VCC = 3.3 V
  • Up to 16-MHz Clock Rate for up to 1-Mbaud Operation With VCC = 2.5 V
  • Up to 10-MHz Clock Rate for up to 625-kbaud Operation With VCC = 1.8 V
  • In the TL16C450 Mode, Hold and Shift Registers Eliminate the Need for Precise Synchronization Between the CPU and Serial Data
  • Programmable Baud Rate Generator Allows Division of Any Input Reference Clock by 1 to (216 - 1) and Generates an Internal 16 × Clock
  • Standard Asynchronous Communication Bits (Start, Stop, and Parity) Added to or Deleted From the Serial Data Stream
  • 5-V, 3.3-V, 2.5-V, and 1.8 V Operation
  • Independent Receiver Clock Input
  • Transmit, Receive, Line Status, and Data Set Interrupts Independently Controlled
  • Fully Programmable Serial Interface Characteristics:
    • 5-, 6-, 7-, or 8-Bit Characters
    • Even-, Odd-, or No-Parity Bit Generation and Detection
    • 1-, 1 ½, or 2-Stop Bit Generation
    • Baud Generation (dc to 1 Mbit/s)
  • False-Start Bit Detection
  • Complete Status Reporting Capabilities
  • 3-State Output TTL Drive Capabilities for Bidirectional Data Bus and Control Bus
  • Line Break Generation and Detection
  • Internal Diagnostic Capabilities:
    • Loopback Controls for Communications Link Fault Isolation
    • Break, Parity, Overrun, and Framing Error Simulation
  • Fully Prioritized Interrupt System Controls
  • Modem Control Functions (CTS, RTS, DSR, DTR, RI, and DCD)
  • Available in 44-Pin PLCC (FN) or 32-Pin QFN (RHB) Packages
  • Each UART's Internal Register Set May Be Written Concurrently to Save Setup Time
  • Multi-Function Output (MF) Allows Users to Select Among Several Functions, Saving Package Pins
  • APPLICATIONS
    • Point-of-Sale Terminals
    • Gaming Terminals
    • Portable Applications
    • Router Control
    • Cellular Data
    • Factory Automation

open-in-new Find other UARTs

Description

The TL16C2552 is a dual universal asynchronous receiver and transmitter (UART). It incorporates the functionality of two TL16C550D UARTs, each UART having its own register set and FIFOs. The two UARTs share only the data bus interface and clock source, otherwise they operate independently. Another name for the UART function is Asynchronous Communications Element (ACE), and these terms will be used interchangeably. The bulk of this document describes the behavior of each ACE, with the understanding that two such devices are incorporated into the TL16C2552.

Each ACE is a speed and voltage range upgrade of the TL16C550C, which in turn is a functional upgrade of the TL16C450. Functionally equivalent to the TL16C450 on power up or reset (single character or TL16C450 mode), each ACE can be placed in an alternate FIFO mode. This relieves the CPU of excessive software overhead by buffering received and to be transmitted characters. Each receiver and transmitter store up to 16 bytes in their respective FIFOs, with the receive FIFO including three additional bits per byte for error status. In the FIFO mode, a selectable autoflow control feature can significantly reduce software overload and increase system efficiency by automatically controlling serial data flow using handshakes between the RTS output and CTS input, thus eliminating overruns in the receive FIFO.

Each ACE performs serial-to-parallel conversions on data received from a peripheral device or modem and stores the parallel data in its receive buffer or FIFO, and each ACE performs parallel-to-serial conversions on data sent from its CPU after storing the parallel data in its transmit buffer or FIFO. The CPU can read the status of either ACE at any time. Each ACE includes complete modem control capability and a processor interrupt system that can be tailored to the application.

Each ACE includes a programmable baud rate generator capable of dividing a reference clock with divisors of from 1 to 65535, thus producing a 16× internal reference clock for the transmitter and receiver logic. Each ACE accommodates up to a 1.5-Mbaud serial data rate (24-MHz input clock). As a reference point, that speed would generate a 667-ns bit time and a 6.7-µs character time (for 8,N,1 serial data), with the internal clock running at 24 MHz.

Each ACE has a TXRDY and RXRDY output that can be used to interface to a DMA controller.

open-in-new Find other UARTs
Download

Technical documentation

star = Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 2
Type Title Date
* Data sheet 1.8-V to 5-V DUAL UART WITH 16-BYTE FIFOS datasheet (Rev. A) Jun. 15, 2006
More literature UART Quick Reference Card (Rev. D) Apr. 09, 2008

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Design tools & simulation

SIMULATION MODEL Download
SLLM024.ZIP (51 KB) - IBIS Model
SIMULATION MODEL Download
SLLM025.ZIP (51 KB) - IBIS Model
SIMULATION MODEL Download
SLLM026.ZIP (52 KB) - IBIS Model
SIMULATION TOOL Download
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Features
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
SIMULATION TOOL Download
SPICE-based analog simulation program
TINA-TI TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
document-generic User guide

CAD/CAE symbols

Package Pins Download
PLCC (FN) 44 View options

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos