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TL28L92

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3.3-V/5-V Dual Universal Asynchronous Receiver/Transmitter

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Data sheet

TL28L92

ACTIVE
Data sheet Order now

Product details

Number of channels 2 FIFO (Byte) 16 Rx FIFO trigger levels (#) 4 Tx FIFO trigger levels (#) 4 Programmable FIFO trigger levels Yes CPU interface X86 or 68K Baud rate at Vcc = 3.3 V & with 16x sampling (max) (MBps) 1 Baud rate at Vcc = 5 V & with 16x sampling (max) (MBps) 1 Operating voltage (V) 3.3, 5 Auto RTS/CTS Yes Rating Catalog Operating temperature range (°C) -40 to 85
Number of channels 2 FIFO (Byte) 16 Rx FIFO trigger levels (#) 4 Tx FIFO trigger levels (#) 4 Programmable FIFO trigger levels Yes CPU interface X86 or 68K Baud rate at Vcc = 3.3 V & with 16x sampling (max) (MBps) 1 Baud rate at Vcc = 5 V & with 16x sampling (max) (MBps) 1 Operating voltage (V) 3.3, 5 Auto RTS/CTS Yes Rating Catalog Operating temperature range (°C) -40 to 85
QFP (FR) 44 153.76 mm² 12.4 x 12.4
  • SC28L92 Pin Compatible
  • 3.3 V to 5.0 V, –40°C to 85°C and 68xxx or
    80xxx Bus Interface
  • Dual Full-Duplex Independent Asynchronous
    Receiver/Transmitters 16 Character FIFOs for
    Each Receiver and Transmitter
  • Pin Programming Selects 68xxx or 80xxx Bus
    Interface
  • Programmable Data Format
    • 5 Data to 8 Data Bits Plus Parity
    • Odd, Even, No Parity or Force Parity
    • 1 Stop, 1.5 Stop or 2 Stop Bits
      Programmable in 1/16-Bit Increments
  • 16-Bit Programmable Counter/Timer
  • Programmable Baud Rate for Each Receiver
    and Transmitter Selectable From:
    • 28 Fixed Rates: 50 Bd to 230.4 kBd
    • Other Baud Rates to 1 MHz at 16×
    • Programmable User-Defined Rates Derived
      From a Programmable Counter/Timer
  • External 1× or 16× Clock
  • Parity, Framing, and Overrun Error Detection
  • False Start Bit Detection
  • Line Break Detection and Generation
  • Programmable Channel Mode
    • Normal (Full-Duplex)
    • Automatic Echo
    • Local Loopback
    • Remote Loopback
    • Multi-Drop Mode (Also Called Wake-Up or
      9-Bit)
  • Multi-Function 7-Bit Input Port
    (Includes IACKN)
    • Can Serve as Clock or Control Inputs
    • Change of State Detection on Four Inputs
      Inputs Have Typically > 100 k Pullup Resistors
    • Change of State Detectors for Modem Control
  • Multi-Function 8-Bit Output Port
    • Individual Bit Set/Reset Capability
    • Outputs Can Be Programmed to Be
      Status/Interrupt Signals
    • FIFO Status for DMA Interface
  • Versatile Interrupt System
    • Single Interrupt Output With Eight Maskable
      Interrupting Conditions
    • Output Port Can be Configured to Provide a
      Total of up to Five Separate Interrupt
      Outputs That May be Wire ORed
    • Each FIFO Can be Programmed for Four
      Different Interrupt Levels
    • Watchdog Timer for Each Receiver
  • Maximum Data Transfer Rates: 1× – 1 Mbit/s,
    16× – 1 Mbit/s
  • Automatic Wake-Up Mode for Multi-Drop Applications
  • Start-End Break Interrupt/Status
  • Detects Break Which Originates in the Middle
    of a Character
  • On-Chip Crystal Oscillator
  • Powerdown Mode
  • Receiver Time-Out Mode
  • Single 3.3 V or 5 V Power Supply
  • Powers up to Emulate SC26C92
  • Meets or Exceeds JEDEC 14C ESD
    Requirements
  • SC28L92 Pin Compatible
  • 3.3 V to 5.0 V, –40°C to 85°C and 68xxx or
    80xxx Bus Interface
  • Dual Full-Duplex Independent Asynchronous
    Receiver/Transmitters 16 Character FIFOs for
    Each Receiver and Transmitter
  • Pin Programming Selects 68xxx or 80xxx Bus
    Interface
  • Programmable Data Format
    • 5 Data to 8 Data Bits Plus Parity
    • Odd, Even, No Parity or Force Parity
    • 1 Stop, 1.5 Stop or 2 Stop Bits
      Programmable in 1/16-Bit Increments
  • 16-Bit Programmable Counter/Timer
  • Programmable Baud Rate for Each Receiver
    and Transmitter Selectable From:
    • 28 Fixed Rates: 50 Bd to 230.4 kBd
    • Other Baud Rates to 1 MHz at 16×
    • Programmable User-Defined Rates Derived
      From a Programmable Counter/Timer
  • External 1× or 16× Clock
  • Parity, Framing, and Overrun Error Detection
  • False Start Bit Detection
  • Line Break Detection and Generation
  • Programmable Channel Mode
    • Normal (Full-Duplex)
    • Automatic Echo
    • Local Loopback
    • Remote Loopback
    • Multi-Drop Mode (Also Called Wake-Up or
      9-Bit)
  • Multi-Function 7-Bit Input Port
    (Includes IACKN)
    • Can Serve as Clock or Control Inputs
    • Change of State Detection on Four Inputs
      Inputs Have Typically > 100 k Pullup Resistors
    • Change of State Detectors for Modem Control
  • Multi-Function 8-Bit Output Port
    • Individual Bit Set/Reset Capability
    • Outputs Can Be Programmed to Be
      Status/Interrupt Signals
    • FIFO Status for DMA Interface
  • Versatile Interrupt System
    • Single Interrupt Output With Eight Maskable
      Interrupting Conditions
    • Output Port Can be Configured to Provide a
      Total of up to Five Separate Interrupt
      Outputs That May be Wire ORed
    • Each FIFO Can be Programmed for Four
      Different Interrupt Levels
    • Watchdog Timer for Each Receiver
  • Maximum Data Transfer Rates: 1× – 1 Mbit/s,
    16× – 1 Mbit/s
  • Automatic Wake-Up Mode for Multi-Drop Applications
  • Start-End Break Interrupt/Status
  • Detects Break Which Originates in the Middle
    of a Character
  • On-Chip Crystal Oscillator
  • Powerdown Mode
  • Receiver Time-Out Mode
  • Single 3.3 V or 5 V Power Supply
  • Powers up to Emulate SC26C92
  • Meets or Exceeds JEDEC 14C ESD
    Requirements

The TL28L92 is a pin and function replacement for the SC26C92 operating at 3.3 V or 5 V supply with added features and deeper FIFOs. Its configuration on power-up is that of the SC26C92. Its differences from the SC26C92 are: 16 character receiver, 16 character transmit FIFOs, watchdog timer for each receiver, mode register 0 is added, extended baud rate and overall faster speeds, programmable receiver and transmitter interrupts.

Pin programming will allow the device to operate with either the Motorola or Intel bus interface. The bit 3 of the MR0A register allows the device to operate in an 8 byte FIFO mode if strict compliance with the SC26C92 FIFO structure is required.

The Texas Instruments TL28L92 Dual Universal Asynchronous Receiver/Transmitter (DUART) is a single-chip CMOS-LSI communications device that provides two full-duplex asynchronous receiver/transmitter channels in a single package. It interfaces directly with microprocessors and may be used in a polled or interrupt driven system with modem and DMA interface.

The operating mode and data format of each channel can be programmed independently. Additionally, each receiver and transmitter can select its operating speed as one of 28 fixed baud rates; a 16× clock derived from a programmable counter/timer, or an external 1× or 16× clock. The baud rate generator and counter/timer can operate directly from a crystal or from external clock inputs. The ability to independently program the operating speed of the receiver and transmitter make the DUART particularly attractive for dual-speed channel applications such as clustered terminal systems.

Each receiver and transmitter is buffered by 8 or 16 character FIFOs to minimize the potential of receiver overrun, transmitter underrun and to reduce interrupt overhead in interrupt driven systems. In addition, a flow control capability is provided via RTS/CTS signaling to disable a remote transmitter when the receiver buffer is full. Also provided on the TL28L92 are a multipurpose 7-bit input port and a multipurpose 8-bit output port. These can be used as general purpose I/O ports or can be assigned specific functions (such as clock inputs or status/interrupt outputs) under program control.

The TL28L92 is available now in 44-pin QFP (FR), and will be available 2Q09 in 48-pin QFN (RGZ).

The TL28L92 is a pin and function replacement for the SC26C92 operating at 3.3 V or 5 V supply with added features and deeper FIFOs. Its configuration on power-up is that of the SC26C92. Its differences from the SC26C92 are: 16 character receiver, 16 character transmit FIFOs, watchdog timer for each receiver, mode register 0 is added, extended baud rate and overall faster speeds, programmable receiver and transmitter interrupts.

Pin programming will allow the device to operate with either the Motorola or Intel bus interface. The bit 3 of the MR0A register allows the device to operate in an 8 byte FIFO mode if strict compliance with the SC26C92 FIFO structure is required.

The Texas Instruments TL28L92 Dual Universal Asynchronous Receiver/Transmitter (DUART) is a single-chip CMOS-LSI communications device that provides two full-duplex asynchronous receiver/transmitter channels in a single package. It interfaces directly with microprocessors and may be used in a polled or interrupt driven system with modem and DMA interface.

The operating mode and data format of each channel can be programmed independently. Additionally, each receiver and transmitter can select its operating speed as one of 28 fixed baud rates; a 16× clock derived from a programmable counter/timer, or an external 1× or 16× clock. The baud rate generator and counter/timer can operate directly from a crystal or from external clock inputs. The ability to independently program the operating speed of the receiver and transmitter make the DUART particularly attractive for dual-speed channel applications such as clustered terminal systems.

Each receiver and transmitter is buffered by 8 or 16 character FIFOs to minimize the potential of receiver overrun, transmitter underrun and to reduce interrupt overhead in interrupt driven systems. In addition, a flow control capability is provided via RTS/CTS signaling to disable a remote transmitter when the receiver buffer is full. Also provided on the TL28L92 are a multipurpose 7-bit input port and a multipurpose 8-bit output port. These can be used as general purpose I/O ports or can be assigned specific functions (such as clock inputs or status/interrupt outputs) under program control.

The TL28L92 is available now in 44-pin QFP (FR), and will be available 2Q09 in 48-pin QFN (RGZ).
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* Data sheet 3.3-V/5-V Dual Universal Asynchronous Receiver/Transmitter datasheet (Rev. B) 28 Aug 2009

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