Product details

DSP type 1 C64x DSP (max) (MHz) 500 CPU 32-/64-bit Operating system DSP/BIOS Rating Catalog Operating temperature range (°C) -40 to 105
DSP type 1 C64x DSP (max) (MHz) 500 CPU 32-/64-bit Operating system DSP/BIOS Rating Catalog Operating temperature range (°C) -40 to 105
OMFCBGA (GTS) 288 529 mm² 23 x 23 OMFCBGA (ZTS) 288 529 mm² 23 x 23
  • High-Performance Fixed-Point Digital Signal Processor (TMS320C6413/C6410)
    • TMS320C6413
      • 2-ns Instruction Cycle Time
      • 500-MHz Clock Rate
      • 4000 MIPS
    • TMS320C6410
      • 2.5-ns Instruction Cycle Time
      • 400-MHz Clock Rate
      • 3200 MIPS
    • Eight 32-Bit Instructions/Cycle
    • Fully Software-Compatible With C64x™
    • Extended Temperature Devices Available
  • VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x™ DSP Core
    • Eight Highly Independent Functional Units With VelociTI.2™ Extensions:
      • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
      • Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
    • Load-Store Architecture With Non-Aligned Support
    • 64 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
  • Instruction Set Features
    • Byte-Addressable (8-/16-/32-/64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • VelociTI.2™ Increased Orthogonality
  • VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x™ DSP Core
  • L1/L2 Memory Architecture
    • 128K-Bit (16K-Byte) L1P Program Cache (Direct Mapped)
    • 128K-Bit (16K-Byte) L1D Data Cache (2-Way Set-Associative)
    • 2M-Bit (256K-Byte) L2 Unified Mapped RAM/Cache [C6413] (Flexible RAM/Cache Allocation)
    • 1M-Bit (128K-Byte) L2 Unified Mapped RAM/Cache [C6410] (Flexible RAM/Cache Allocation)
  • Endianess: Little Endian, Big Endian
  • 32-Bit External Memory Interface (EMIF)
    • Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO)
    • 512M-Byte Total Addressable External Memory Space
  • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
  • Host-Port Interface (HPI) [32-/16-Bit]
  • Two Multichannel Audio Serial Ports (McASPs) - with Six Serial Data Pins each
  • Two Inter-Integrated Circuit (I2C) Buses
    • Additional GPIO Capability
  • Two Multichannel Buffered Serial Ports
  • Three 32-Bit General-Purpose Timers
  • Sixteen General-Purpose I/O (GPIO) Pins
  • Flexible PLL Clock Generator
  • On-Chip Fundamental Oscillator
  • IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
  • 288-Pin Ball Grid Array (BGA) Package (GTS and ZTS Suffixes), 1.0-mm Ball Pitch
  • 0.13-µm/6-Level Cu Metal Process (CMOS)
  • 3.3-V I/Os, 1.2-V Internal

VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
TMS320C6000, and C6000 are trademarks of Texas Instruments.

  • High-Performance Fixed-Point Digital Signal Processor (TMS320C6413/C6410)
    • TMS320C6413
      • 2-ns Instruction Cycle Time
      • 500-MHz Clock Rate
      • 4000 MIPS
    • TMS320C6410
      • 2.5-ns Instruction Cycle Time
      • 400-MHz Clock Rate
      • 3200 MIPS
    • Eight 32-Bit Instructions/Cycle
    • Fully Software-Compatible With C64x™
    • Extended Temperature Devices Available
  • VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x™ DSP Core
    • Eight Highly Independent Functional Units With VelociTI.2™ Extensions:
      • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
      • Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
    • Load-Store Architecture With Non-Aligned Support
    • 64 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
  • Instruction Set Features
    • Byte-Addressable (8-/16-/32-/64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • VelociTI.2™ Increased Orthogonality
  • VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x™ DSP Core
  • L1/L2 Memory Architecture
    • 128K-Bit (16K-Byte) L1P Program Cache (Direct Mapped)
    • 128K-Bit (16K-Byte) L1D Data Cache (2-Way Set-Associative)
    • 2M-Bit (256K-Byte) L2 Unified Mapped RAM/Cache [C6413] (Flexible RAM/Cache Allocation)
    • 1M-Bit (128K-Byte) L2 Unified Mapped RAM/Cache [C6410] (Flexible RAM/Cache Allocation)
  • Endianess: Little Endian, Big Endian
  • 32-Bit External Memory Interface (EMIF)
    • Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO)
    • 512M-Byte Total Addressable External Memory Space
  • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
  • Host-Port Interface (HPI) [32-/16-Bit]
  • Two Multichannel Audio Serial Ports (McASPs) - with Six Serial Data Pins each
  • Two Inter-Integrated Circuit (I2C) Buses
    • Additional GPIO Capability
  • Two Multichannel Buffered Serial Ports
  • Three 32-Bit General-Purpose Timers
  • Sixteen General-Purpose I/O (GPIO) Pins
  • Flexible PLL Clock Generator
  • On-Chip Fundamental Oscillator
  • IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
  • 288-Pin Ball Grid Array (BGA) Package (GTS and ZTS Suffixes), 1.0-mm Ball Pitch
  • 0.13-µm/6-Level Cu Metal Process (CMOS)
  • 3.3-V I/Os, 1.2-V Internal

VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
TMS320C6000, and C6000 are trademarks of Texas Instruments.

The TMS320C64x™ DSPs (including the TMS320C6413, TMS320C6410 devices) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The TMS320C6413 and TMS320C6410 (C6413 and C6410) devices are based on the second-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture (VelociTI.2™) developed by Texas Instruments (TI)™ The high-performance, lower-cost C6413/C6410 DSPs enable customers to reduce system costs for telecom, medical, industrial, office, and photo lab equipment. The C64x™ is a code-compatible member of the C6000™ DSP platform.

With performance of up to 4000 million instructions per second (MIPS) at a clock rate of 500 MHz, the C6413 device offers cost-effective solutions to high-performance DSP programming challenges.

With performance of up to 3200 million instructions per second (MIPS) at a clock rate of 400 MHz, the C6410 device offers cost-effective solutions to high-performance DSP programming challenges. The C6410 device also provides excellent value for packet telephony and for other cost-sensitive applications demanding high performance. The C6410 device also provides excellent value for packet telephony and to other cost-sensitive applications demanding high performance

The C6413/C6410 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x™ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs)— with VelociTI.2™ extensions. The VelociTI.2™ extensions in the eight functional units include new instructions to accelerate the performance in video and imaging applications and extend the parallelism of the VelociTI™ architecture. The C6413 can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2000 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4000 MMACS. The C6410 can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 1600 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 3200 MMACS. The C6413/C6410 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000™ DSP platform devices.

The C6413/C6410 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 2-Mbit memory space that is shared between program and data space [for C6413 device] and the Level 2 memory/cache (L2) consists of an 1-Mbit memory space that is shared between program and data space [for C6410 device]. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes: two multichannel buffered audio serial ports (McASPs); two inter-integrated circuit bus modules (I2Cs) ; two multichannel buffered serial ports (McBSPs); three 32-bit general-purpose timers; a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a 16-pin general-purpose input/output port (GP0) with programmable interrupt/event generation modes; and a 32-bit glueless external memory interface (EMIFA), which is capable of interfacing to synchronous and asynchronous memories and peripherals.

The McASP port supports one transmit and one receive clock zone, with eight serial data pins which can be individually allocated to any of the two zones. The serial port supports time-division multiplexing on each pin from 2 to 32 time slots. The C6413/C6410 has sufficient bandwidth to support all 8 serial data pins transmitting a 192-kHz stereo signal. Serial data in each zone may be transmitted and received on multiple serial data pins simultaneously and formatted in a multitude of variations on the Philips Inter-IC Sound (I2S) format.

In addition, the McASP transmitter may be programmed to output multiple S/PDIF, IEC60958, AES-3, CP-430 encoded data channels simultaneously, with a single RAM containing the full implementation of user data and channel status fields.

McASP also provides extensive error-checking and recovery features, such as the bad clock detection circuit for each high-frequency master clock which verifies that the master clock is within a programmed frequency range.

The I2C ports on the TMS320C6413/C6410 allows the DSP to easily control peripheral devices and communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to communicate with serial peripheral interface (SPI) mode peripheral devices.

TheC6413/C6410 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

The TMS320C64x™ DSPs (including the TMS320C6413, TMS320C6410 devices) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The TMS320C6413 and TMS320C6410 (C6413 and C6410) devices are based on the second-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture (VelociTI.2™) developed by Texas Instruments (TI)™ The high-performance, lower-cost C6413/C6410 DSPs enable customers to reduce system costs for telecom, medical, industrial, office, and photo lab equipment. The C64x™ is a code-compatible member of the C6000™ DSP platform.

With performance of up to 4000 million instructions per second (MIPS) at a clock rate of 500 MHz, the C6413 device offers cost-effective solutions to high-performance DSP programming challenges.

With performance of up to 3200 million instructions per second (MIPS) at a clock rate of 400 MHz, the C6410 device offers cost-effective solutions to high-performance DSP programming challenges. The C6410 device also provides excellent value for packet telephony and for other cost-sensitive applications demanding high performance. The C6410 device also provides excellent value for packet telephony and to other cost-sensitive applications demanding high performance

The C6413/C6410 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x™ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs)— with VelociTI.2™ extensions. The VelociTI.2™ extensions in the eight functional units include new instructions to accelerate the performance in video and imaging applications and extend the parallelism of the VelociTI™ architecture. The C6413 can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2000 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4000 MMACS. The C6410 can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 1600 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 3200 MMACS. The C6413/C6410 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000™ DSP platform devices.

The C6413/C6410 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 2-Mbit memory space that is shared between program and data space [for C6413 device] and the Level 2 memory/cache (L2) consists of an 1-Mbit memory space that is shared between program and data space [for C6410 device]. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes: two multichannel buffered audio serial ports (McASPs); two inter-integrated circuit bus modules (I2Cs) ; two multichannel buffered serial ports (McBSPs); three 32-bit general-purpose timers; a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a 16-pin general-purpose input/output port (GP0) with programmable interrupt/event generation modes; and a 32-bit glueless external memory interface (EMIFA), which is capable of interfacing to synchronous and asynchronous memories and peripherals.

The McASP port supports one transmit and one receive clock zone, with eight serial data pins which can be individually allocated to any of the two zones. The serial port supports time-division multiplexing on each pin from 2 to 32 time slots. The C6413/C6410 has sufficient bandwidth to support all 8 serial data pins transmitting a 192-kHz stereo signal. Serial data in each zone may be transmitted and received on multiple serial data pins simultaneously and formatted in a multitude of variations on the Philips Inter-IC Sound (I2S) format.

In addition, the McASP transmitter may be programmed to output multiple S/PDIF, IEC60958, AES-3, CP-430 encoded data channels simultaneously, with a single RAM containing the full implementation of user data and channel status fields.

McASP also provides extensive error-checking and recovery features, such as the bad clock detection circuit for each high-frequency master clock which verifies that the master clock is within a programmed frequency range.

The I2C ports on the TMS320C6413/C6410 allows the DSP to easily control peripheral devices and communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to communicate with serial peripheral interface (SPI) mode peripheral devices.

TheC6413/C6410 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

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Technical documentation

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Type Title Date
* Data sheet TMS320C6413, TMS320C6410 Fixed-Point Digital Signal Processors datasheet (Rev. F) 16 Jan 2006
* Errata TMS320C6413, TMS320C6410 DSPs Silicon Errata (Rev. C) 24 Nov 2004
Application note How to Migrate CCS 3.x Projects to the Latest CCS (Rev. A) PDF | HTML 19 May 2021
User guide TMS320 DSP/BIOS v5.42 User's Guide (Rev. I) 09 Oct 2012
User guide TMS320C6000 Assembly Language Tools v 7.4 User's Guide (Rev. W) 21 Aug 2012
User guide TMS320C6000 Optimizing Compiler v 7.4 User's Guide (Rev. U) 21 Aug 2012
User guide Emulation and Trace Headers Technical Reference Manual (Rev. I) 09 Aug 2012
Application note Introduction to TMS320C6000 DSP Optimization 06 Oct 2011
User guide TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (Rev. J) 30 Jul 2010
User guide TMS320C6000 Assembly Language Tools v 7.0 User's Guide (Rev. S) 18 Mar 2010
User guide TMS320C6000 Optimizing Compiler v 7.0 User's Guide (Rev. Q) 18 Mar 2010
User guide TMS320C6000 DSP Peripherals Overview Reference Guide (Rev. Q) 02 Jul 2009
Application note Common Object File Format (COFF) 15 Apr 2009
User guide TMS320C6000 DSP Multi-channel Audio Serial Port (McASP) Reference Guide (Rev. J) 20 Nov 2008
User guide TMS320C6000 Assembly Language Tools v 6.1 User's Guide (Rev. Q) 15 May 2008
User guide TMS320C6000 Optimizing Compiler v 6.1 User's Guide (Rev. O) 15 May 2008
Application note TMS320C6000 EMIF-to-External SDRAM Interface (Rev. E) 04 Sep 2007
Application note Thermal Considerations for the DM64xx, DM64x, and C6000 Devices 20 May 2007
User guide TMS320C6000 DSP External Memory Interface (EMIF) Reference Guide (Rev. E) 11 Apr 2007
Product overview TMS320C6000 DSP TCP/IP Stack Software (Rev. C) 04 Apr 2007
User guide TMS320C6000 DSP Inter-Integrated Circuit (I2C) Module Reference Guide (Rev. D) 26 Mar 2007
User guide TMS320C6000 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (Rev. G) 14 Dec 2006
User guide TMS320C6000 DSP Enhanced Direct Memory Access (EDMA) Controller Reference Guide (Rev. C) 15 Nov 2006
User guide TMS320C64x DSP Two-Level Internal Memory Reference Guide (Rev. C) 28 Feb 2006
User guide TMS320C6000 DSP Host-Post Interface (HPI) Reference Guide (Rev. C) 01 Jan 2006
Application note TMS320C6413 Hardware Designer's Resource Guide (Rev. D) 24 Oct 2005
Application note Migrating from TMS320C64x to TMS320C64x+ (Rev. A) 20 Oct 2005
User guide TMS320C6000 DSP Power-Down Logic and Modes Reference Guide (Rev. C) 01 Mar 2005
User guide TMS320C6000 DSP 32-bit Timer Reference Guide (Rev. B) 25 Jan 2005
Application note TMS320C6410/13 Power Consumption Summary 20 Sep 2004
Application note Use and Handling of Semiconductor Packages With ENIG Pad Finishes 31 Aug 2004
User guide TMS320C6000 Chip Support Library API Reference Guide (Rev. J) 13 Aug 2004
User guide TMS320C6410/13/18 DSP Inter-Integrated Circuit (I2C) Module Addendum to SPRU175 (Rev. A) 13 Aug 2004
Application note TMS320C64x Reference Design 12 May 2004
Application note TMS320C6000 Tools: Vector Table and Boot ROM Creation (Rev. D) 26 Apr 2004
Application note TMS320C6000 Board Design: Considerations for Debug (Rev. C) 21 Apr 2004
User guide TMS320C6000 DSP General-Purpose Input/Output (GPIO) Reference Guide (Rev. A) 25 Mar 2004
Application note TMS320C6000 McBSP Initialization (Rev. C) 08 Mar 2004
Application note TMS320C6000 EDMA IO Scheduling and Performance 05 Mar 2004
Application note TMS320C64x EDMA Performance Data 05 Mar 2004
Application note TMS320C64x EDMA Architecture 03 Mar 2004
Application note TMS320C64x DSP Host Port Interface (HPI) Performance 24 Oct 2003
Application note TMS320C6000 EMIF to TMS320C6000 Host Port Interface (Rev. B) 12 Sep 2003
User guide TMS320C6000 DSP Designing for JTAG Emulation Reference Guide 31 Jul 2003
User guide TMS320C6000 DSP Cache User's Guide (Rev. A) 05 May 2003
Application note Using IBIS Models for Timing Analysis (Rev. A) 15 Apr 2003
Application note TMS320C6000 McBSP Interface to an ST-BUS Device (Rev. B) 04 Jun 2002
Application note TMS320C6000 Board Design for JTAG (Rev. C) 02 Apr 2002
Application note TMS320C6000 EMIF to External Flash Memory (Rev. A) 13 Feb 2002
Application note Cache Usage in High-Performance DSP Applications with the TMS320C64x 13 Dec 2001
Application note Using a TMS320C6000 McBSP for Data Packing (Rev. A) 31 Oct 2001
Application note TMS320C6000 Enhanced DMA: Example Applications (Rev. A) 24 Oct 2001
Application note TMS320C6000 Host Port to MC68360 Interface (Rev. A) 30 Sep 2001
Application note TMS320C6000 EMIF to External Asynchronous SRAM Interface (Rev. A) 31 Aug 2001
Application note TMS320C6000 Host Port to the i80960 Microprocessors Interface (Rev. A) 31 Aug 2001
Application note Using the TMS320C6000 McBSP as a High Speed Communication Port (Rev. A) 31 Aug 2001
Application note TMS320C6000 McBSP to Voice Band Audio Processor (VBAP) Interface (Rev. A) 23 Jul 2001
Application note TMS320C6000 McBSP: AC'97 Codec Interface (TLV320AIC27) (Rev. A) 10 Jul 2001
Application note TMS320C6000 McBSP: Interface to SPI ROM (Rev. C) 30 Jun 2001
Application note TMS320C6000 Host Port to MPC860 Interface (Rev. A) 21 Jun 2001
Application note TMS320C6000 McBSP: IOM-2 Interface (Rev. A) 21 May 2001
Application note Circular Buffering on TMS320C6000 (Rev. A) 12 Sep 2000
Application note TMS320C6000 McBSP as a TDM Highway (Rev. A) 11 Sep 2000
Application note TMS320C6000 Multichannel Communications System Interface 03 Feb 2000
Application note TMS320C6000 u-Law and a-Law Companding with Software or the McBSP 02 Feb 2000
Application note General Guide to Implement Logarithmic and Exponential Operations on Fixed-Point 31 Jan 2000
Application note TMS320C6000 C Compiler: C Implementation of Intrinsics 07 Dec 1999
Application note TMS320C6000 HPI Boot Operation 06 Jan 1999

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Debug probe

TMDSEMU560V2STM-U — XDS560™ software v2 system trace USB debug probe

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).  Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

Not available on TI.com
Debug probe

TMDSEMU560V2STM-UE — XDS560v2 System Trace USB & Ethernet Debug Probe

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

Not available on TI.com
Driver or library

SPRC264 — TMS320C5000/6000 Image Library (IMGLIB)

C5000/6000 Image Processing Library (IMGLIB) is an optimized image/video processing function library for C programmers. It includes C-callable general-purpose image/video processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
Driver or library

SPRC265 — TMS320C6000 DSP Library (DSPLIB)

TMS320C6000 Digital Signal Processor Library (DSPLIB) is a platform-optimized DSP function library for C programmers. It includes C-callable, general-purpose signal-processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
Driver or library

TELECOMLIB — Telecom and Media Libraries - FAXLIB, VoLIB and AEC/AER for TMS320C64x+ and TMS320C55x Processors

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)
IDE, configuration, compiler or debugger

CCSTUDIO Code Composer Studio™ integrated development environment (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It comprises a suite of tools used to develop and debug embedded applications.  Code Composer Studio is available for download across Windows®, Linux® and macOS® desktops. It can also (...)

Supported products & hardware

Supported products & hardware

This design resource supports most products in these categories.

Check the product details page to verify support.

Launch Download options
Simulation model

C6413 GTS BSDL Model (Rev. B)

SPRM150B.ZIP (7 KB) - BSDL Model
Simulation model

C6413 GTS IBIS Model (Rev. A)

SPRM151A.ZIP (96 KB) - IBIS Model
Schematic

TMS320C6413 ORCAD Symbol

SPRC173.ZIP (5 KB)
Package Pins CAD symbols, footprints & 3D models
OMFCBGA (GTS) 288 Ultra Librarian
OMFCBGA (ZTS) 288 Ultra Librarian

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Information included:
  • Fab location
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