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Product details

Parameters

DSP 1 C64x On-chip L2 cache/RAM 512 KB Total on-chip memory (KB) 544 DRAM SDRAM Serial I/O McBSP, McASP, I2C I2C 2 Approx. price (US$) 42.37 | 1ku Operating temperature range (C) -40 to 105, 0 to 90 Rating Catalog open-in-new Find other C6000 floating-point DSPs

Package | Pins | Size

FCBGA (GTS) 288 529 mm² 23 x 23 FCBGA (ZTS) 288 529 mm² 23 x 23 open-in-new Find other C6000 floating-point DSPs

Features

  • High-Performance Fixed-Point Digital Signal Processor (TMS320C6418)
    • Commercial Temperature Device
      • 1.67-ns Instruction Cycle Time
      • 600-MHz Clock Rate
      • 4800 MIPS
    • Extended Temperature Device
      • 2-ns Instruction Cycle Time
      • 500-MHz Clock Rate
      • 4000 MIPS
    • Eight 32-Bit Instructions/Cycle
    • Fully Software-Compatible With C64x™
  • VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x™ DSP Core
    • Eight Highly Independent Functional Units With VelociTI.2™ Extensions:
      • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
      • Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
    • Load-Store Architecture With Non-Aligned Support
    • 64 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
  • Instruction Set Features
    • Byte-Addressable (8-/16-/32-/64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • VelociTI.2™ Increased Orthogonality
  • VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x™ DSP Core
  • Viterbi Decoder Coprocessor (VCP)
    • Supports Over 500 7.95-Kbps AMR
    • Programmable Code Parameters
  • L1/L2 Memory Architecture
    • 128K-Bit (16K-Byte) L1P Program Cache (Direct Mapped)
    • 128K-Bit (16K-Byte) L1D Data Cache (2-Way Set-Associative)
    • 4M-Bit (512K-Byte) L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation)
  • Endianess: Little Endian, Big Endian
  • 32-Bit External Memory Interface (EMIF)
    • Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO)
    • 512M-Byte Total Addressable External Memory Space
  • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
  • Host-Port Interface (HPI) [32-/16-Bit]
  • Two Multichannel Audio Serial Ports (McASPs) - with Six Serial Data Pins each
  • Two Inter-Integrated Circuit (I2C) Buses
    • Additional GPIO Capability
  • Two Multichannel Buffered Serial Ports
  • Three 32-Bit General-Purpose Timers
  • Sixteen General-Purpose I/O (GPIO) Pins
  • Flexible PLL Clock Generator
  • On-Chip Fundamental Oscillator
  • IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
  • 288-Pin Ball Grid Array (BGA) Package (GTS and ZTS Suffixes), 1.0-mm Ball Pitch
  • 0.13-µm/6-Level Cu Metal Process (CMOS)
  • 3.3-V I/Os, 1.4-V Internal (-600)
  • 3.3-V I/Os, 1.2-V Internal (A-500)

VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
TMS320C6000, and C6000 are trademarks of Texas Instruments.

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Description

The TMS320C64x™ DSPs (including the TMS320C6418 device) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The TMS320C6418 (C6418) device is based on the second-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture (VelociTI.2™) developed by Texas Instruments (TI). The high-performance, lower-cost C6418 DSP enables customers to reduce system costs for telecom, software radio, Digital Terrestrial Television Broadcasting (DTTB), and digital Broadcast Satellite/Communication Satellite (BS/CS) applications. The C64x™ is a code-compatible member of the C6000™ DSP platform.

With performance of up to 4800 million instructions per second (MIPS) at a clock rate of 600 MHz, the C6418 device offers cost-effective solutions to high-performance DSP programming challenges. The C6418 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x. DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs)—with VelociTI.2™ extensions. The VelociTI.2™ extensions in the eight functional units include new instructions to accelerate the performance in video and imaging applications and extend the parallelism of the VelociTI™ architecture. The C6418 can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. The C6418 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000™ DSP platform devices.

The C6418 device has a high-performance embedded coprocessor [Viterbi Decoder Coprocessor (VCP)] that significantly speed up channel-decoding operations on-chip. The VCP operating at CPU clock divided-by-4 can decode over 500 7.95-Kbps adaptive multi-rate (AMR) [K = 9, R = 1/3] voice channels. The VCP supports constraint lengths K = 5, 6, 7, 8, and 9, rates R = 1/2, 1/3, and 1/4, and flexible polynomials, while generating hard decisions or soft decisions. Communications between the VCP and the CPU are carried out through the EDMA controller.

The C6418 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 4-Mbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache (up to 256K bytes), or combinations of the two. The peripheral set includes: two multichannel buffered audio serial ports (McASPs); two inter-integrated circuit bus modules (I2Cs) ; two multichannel buffered serial ports (McBSPs); three 32-bit general-purpose timers; a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a 16-pin general-purpose input/output port (GP0) with programmable interrupt/event generation modes; and a 32-bit glueless external memory interface (EMIFA), which is capable of interfacing to synchronous and asynchronous memories and peripherals.

Each McASP port supports one transmit and one receive clock zone, with six serial data pins which can be individually allocated to any of the two zones. The serial port supports time-division multiplexing on each pin from 2 to 32 time slots. The C6418 has sufficient bandwidth to support all six serial data pins transmitting a 192-kHz stereo signal. Serial data in each zone may be transmitted and received on multiple serial data pins simultaneously and formatted in a multitude of variations on the Philips Inter-IC Sound (I2S) format.

In addition, the McASP transmitter may be programmed to output multiple S/PDIF, IEC60958, AES-3, CP-430 encoded data channels simultaneously, with a single RAM containing the full implementation of user data and channel status fields.

McASP also provides extensive error-checking and recovery features, such as the bad clock detection circuit for each high-frequency master clock which verifies that the master clock is within a programmed frequency range.

The I2C ports on the TMS320C6418 allows the DSP to easily control peripheral devices and communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to communicate with serial peripheral interface (SPI) mode peripheral devices.

The C6418 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

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No design support from TI available

This product does not have ongoing design support from TI for new projects, such as new content or software updates. If available, you will find relevant collateral, software and tools in the product folder. You can also search for archived information in the TI E2ETM support forums.

Technical documentation

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Type Title Date
* Datasheet TMS320C6418 Fixed-Point Digital Signal Processor datasheet (Rev. D) Jan. 17, 2006
* Errata TMS320C6418 Digital Signal Processor Silicon Errata (Rev. A) Nov. 24, 2004
Application notes How to Migrate CCS 3.x Projects to the Latest CCS Feb. 06, 2020
User guides Emulation and Trace Headers Technical Reference Manual (Rev. I) Aug. 09, 2012
Application notes Introduction to TMS320C6000 DSP Optimization Oct. 06, 2011
User guides TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (Rev. J) Jul. 30, 2010
User guides TMS320C6000 DSP Peripherals Overview Reference Guide (Rev. Q) Jul. 02, 2009
User guides TMS320C6000 DSP Multi-channel Audio Serial Port (McASP) Reference Guide (Rev. J) Nov. 20, 2008
Application notes TMS320C6000 EMIF-to-External SDRAM Interface (Rev. E) Sep. 04, 2007
Application notes Thermal Considerations for the DM64xx, DM64x, and C6000 Devices May 20, 2007
User guides TMS320C6000 DSP External Memory Interface (EMIF) Reference Guide (Rev. E) Apr. 11, 2007
More literature TMS320C6000 DSP TCP/IP Stack Software (Rev. C) Apr. 04, 2007
User guides TMS320C6000 DSP Inter-Integrated Circuit (I2C) Module Reference Guide (Rev. D) Mar. 26, 2007
User guides TMS320C6000 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (Rev. G) Dec. 14, 2006
User guides TMS320C6000 DSP Enhanced Direct Memory Access (EDMA) Controller Reference Guide (Rev. C) Nov. 15, 2006
User guides TMS320C64x DSP Two-Level Internal Memory Reference Guide (Rev. C) Feb. 28, 2006
User guides TMS320C6000 DSP Host-Post Interface (HPI) Reference Guide (Rev. C) Jan. 01, 2006
Application notes TMS320C6418 Hardware Designer's Resource Guide (Rev. A) Oct. 25, 2005
Application notes Migrating from TMS320C64x to TMS320C64x+ (Rev. A) Oct. 20, 2005
User guides TMS320C6000 DSP Power-Down Logic and Modes Reference Guide (Rev. C) Mar. 01, 2005
Application notes TMS320C6418 Power Consumption Summary (Rev. A) Feb. 02, 2005
User guides TMS320C6000 DSP 32-bit Timer Reference Guide (Rev. B) Jan. 25, 2005
User guides TMS320C64x DSP Viterbi-Decoder Coprocessor (VCP) Reference Guide (Rev. D) Sep. 20, 2004
Application notes Use and Handling of Semiconductor Packages With ENIG Pad Finishes Aug. 31, 2004
User guides TMS320C6000 Chip Support Library API Reference Guide (Rev. J) Aug. 13, 2004
User guides TMS320C6410/13/18 DSP Inter-Integrated Circuit (I2C) Module Addendum to SPRU175 (Rev. A) Aug. 13, 2004
Application notes TMS320C6000 Tools: Vector Table and Boot ROM Creation (Rev. D) Apr. 26, 2004
Application notes TMS320C6000 Board Design: Considerations for Debug (Rev. C) Apr. 21, 2004
User guides TMS320C6000 DSP General-Purpose Input/Output (GPIO) Reference Guide (Rev. A) Mar. 25, 2004
Application notes TMS320C6000 McBSP Initialization (Rev. C) Mar. 08, 2004
Application notes TMS320C6000 EDMA IO Scheduling and Performance Mar. 05, 2004
Application notes TMS320C64x EDMA Performance Data Mar. 05, 2004
Application notes TMS320C64x EDMA Architecture Mar. 03, 2004
Application notes TMS320C64x DSP Host Port Interface (HPI) Performance Oct. 24, 2003
Application notes Using TMS320C6416 Coprocessors: Viterbi Coprocessor (VCP) (Rev. D) Sep. 15, 2003
Application notes TMS320C6000 EMIF to TMS320C6000 Host Port Interface (Rev. B) Sep. 12, 2003
User guides TMS320C6000 DSP Designing for JTAG Emulation Reference Guide Jul. 31, 2003
Application notes Using IBIS Models for Timing Analysis (Rev. A) Apr. 15, 2003
Application notes TMS320C6000 McBSP Interface to an ST-BUS Device (Rev. B) Jun. 04, 2002
Application notes TMS320C6000 Board Design for JTAG (Rev. C) Apr. 02, 2002
Application notes TMS320C6000 EMIF to External Flash Memory (Rev. A) Feb. 13, 2002
Application notes Cache Usage in High-Performance DSP Applications with the TMS320C64x Dec. 13, 2001
Application notes Using a TMS320C6000 McBSP for Data Packing (Rev. A) Oct. 31, 2001
Application notes TMS320C6000 Enhanced DMA: Example Applications (Rev. A) Oct. 24, 2001
Application notes TMS320C6000 Host Port to MC68360 Interface (Rev. A) Sep. 30, 2001
Application notes TMS320C6000 EMIF to External Asynchronous SRAM Interface (Rev. A) Aug. 31, 2001
Application notes TMS320C6000 Host Port to the i80960 Microprocessors Interface (Rev. A) Aug. 31, 2001
Application notes Using the TMS320C6000 McBSP as a High Speed Communication Port (Rev. A) Aug. 31, 2001
Application notes TMS320C6000 McBSP to Voice Band Audio Processor (VBAP) Interface (Rev. A) Jul. 23, 2001
Application notes TMS320C6000 McBSP: AC'97 Codec Interface (TLV320AIC27) (Rev. A) Jul. 10, 2001
Application notes TMS320C6000 McBSP: Interface to SPI ROM (Rev. C) Jun. 30, 2001
Application notes TMS320C6000 Host Port to MPC860 Interface (Rev. A) Jun. 21, 2001
Application notes TMS320C6000 McBSP: IOM-2 Interface (Rev. A) May 21, 2001
Application notes Circular Buffering on TMS320C6000 (Rev. A) Sep. 12, 2000
Application notes TMS320C6000 McBSP as a TDM Highway (Rev. A) Sep. 11, 2000
Application notes TMS320C6000 Multichannel Communications System Interface Feb. 03, 2000
Application notes TMS320C6000 u-Law and a-Law Companding with Software or the McBSP Feb. 02, 2000
Application notes General Guide to Implement Logarithmic and Exponential Operations on Fixed-Point Jan. 31, 2000
Application notes TMS320C6000 C Compiler: C Implementation of Intrinsics Dec. 07, 1999
Application notes TMS320C6000 McBSP: I2S Interface Sep. 08, 1999
Application notes TMS320C6000 HPI Boot Operation Jan. 06, 1999

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Software development

DEBUG PROBES Download
XDS560v2 System Trace USB Debug Probe
TMDSEMU560V2STM-U The XDS560v2 System Trace is the first model of the XDS560v2 family of high-performance debug probes (emulators) for TI processors. The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).

The (...)

$995.00
Features

XDS560v2 is the latest variant of the XDS560 family of high-performance debug probes (emulators) for TI processors. With the fastest speeds and most features of the entire XDS family, XDS560v2 is the most comprehensive solution to debug TI microcontrollers, processors and wireless connectivity (...)

DEBUG PROBES Download
XDS560v2 System Trace USB & Ethernet Debug Probe
TMDSEMU560V2STM-UE The XDS560v2 System Trace is the first model of the XDS560v2 family of high-performance debug probes (emulators) for TI processors. The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).

The (...)

$1,495.00
Features
  • XDS560v2 is the latest variant of the XDS560 family of high-performance debug probes (emulators) for TI processors. With the fastest speeds and most features of the entire XDS family, XDS560v2 is the most comprehensive solution to debug TI microcontrollers, processors and wireless connectivity (...)

DRIVERS & LIBRARIES Download
TMS320C5000/6000 Image Library (IMGLIB)
SPRC264 C5000/6000 Image Processing Library (IMGLIB) is an optimized image/video processing function library for C programmers. It includes C-callable general-purpose image/video processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
Features

Image Analysis

  • Image boundry and perimeter
  • Morphological operation
  • Edge detection
  • Image Histogram
  • Image thresholding

Image filtering and format conversion

  • Color space conversion
  • Image convolution
  • Image correlation
  • Error diffusion
  • Median filtering
  • Pixel expansion

Image compression and decompression

  • Forward and (...)
DRIVERS & LIBRARIES Download
TMS320C6000 DSP Library (DSPLIB)
SPRC265 TMS320C6000 Digital Signal Processor Library (DSPLIB) is a platform-optimized DSP function library for C programmers. It includes C-callable, general-purpose signal-processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
Features

Optimized DSP routines including functions for:

  • Adaptive filtering
  • Correlation
  • FFT
  • Filtering and convolution: FIR, biquad, IIR, convolution
  • Math: Dot products, max value, min value, etc.
  • Matrix operations
DRIVERS & LIBRARIES Download
Telecom and Media Libraries - FAXLIB, VoLIB and AEC/AER for TMS320C64x+ and TMS320C55x Processors
TELECOMLIB Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be acquired (...)
Features

VoLIB

  • Telogy Software Line Echo Canceller (ECU)
  • Tone Detection Unit (TDU)
  • Caller ID Detection/Generation (CID)
  • Tone Generation Unit (TGU)
  • Voice Activity Detection Unit (VAU)
  • Noise Matching Functions
  • Packet Loss Concealment (PLC)
  • Voice Enhancement Unit (VEU)  

FAXLIB

  • Fax Interface Unit (FIU)
  • Fax Modem (FM)
  • (...)
IDES, CONFIGURATION, COMPILERS & DEBUGGERS Download
C6000 code generation tools - compiler
C6000-CGT — The TI C6000 C/C++ Compiler and Assembly Language Tools support development of applications for TI C6000 Digital Signal Processor platforms, including the C66x multi-core, C674x and C64x+ single-core Digital Signal Processors.
Features
  • Available in C6000 Code Generation Tools starting with v8.3.0:
    • Supports the C++14 Standard ISO/IEC 14882:2014 (C++03 is no longer supported)
  • Available in C6000 Code Generation Tools starting with release v8.2.0:
    • Conversion of floating-point values to unsigned char or short no longer generate RTS (...)
SOFTWARE CODECS Download
Adaptive Digital Technologies DSP VOIP, speech and audio codecs
Provided by Adaptive Digital Technologies, Inc. — Adaptive Digital is a developer of voice quality enhancement algorithms, and best-in-class acoustic echo cancellation software that work with TI DSPs. Adaptive Digital has extensive experience in the algorithm development, implementation, optimization and configuration tuning. They provide solutions (...)
SOFTWARE CODECS Download
CouthIT DSP VoIP, speech, and audio codecs
Provided by Couth Infotech Pvt. Ltd. — Since 1999, CouthIT has been helping customers transform their ideas into real-time robust software solutions. They license specialized, pre-built, highly optimized software modules in the areas of VoIP and speech and audio codecs, and provide software optimization and customization services for (...)
SOFTWARE CODECS Download
Vocal technologies DSP VoIP codecs
Provided by VOCAL Technologies, Ltd. — With over 25 years of assembly and C code development, VOCAL modular software suite is available for a wide variety of TI DSPs. Products include ATAs, VoIP servers and gateways, HPNA-based IPBXs, video surveillance, voice and video conferencing, voice and data RF devices, RoIP gateways, secure (...)

Design tools & simulation

SIMULATION MODELS Download
SPRM162.ZIP (96 KB) - IBIS Model
SIMULATION MODELS Download
SPRM163A.ZIP (7 KB) - BSDL Model

CAD/CAE symbols

Package Pins Download
FCBGA (GTS) 288 View options
FCBGA (ZTS) 288 View options

Ordering & quality

Support & training

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