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Product details

Parameters

DSP 1 C64x+ On-chip L2 cache/RAM 128 KB Total on-chip memory (KB) 304 DRAM DDR2, SDRAM Ethernet MAC 10/100 Serial I/O McBSP, McASP, I2C, UART, VLYNQ I2C 1 Operating temperature range (C) -40 to 105, 0 to 90 UART (SCI) 2 Rating Catalog open-in-new Find other C6000 floating-point DSPs

Package | Pins | Size

BGA (ZDU) 376 529 mm² 23 x 23 NFBGA (ZWT) 361 256 mm² 16 x 16 open-in-new Find other C6000 floating-point DSPs

Features

  • High-Performance Digital Signal Processor (C6424)
    • 2.5-, 2-, 1.67, 1.43-ns Instruction Cycle Time
    • 400-, 500-, 600-MHz C64x+™ Clock Rate
    • Eight 32-Bit C64x+ Instructions/Cycle
    • 3200, 4000, 4800, 5600 MIPS
    • Fully Software-Compatible With C64x
    • Commercial and Automotive (Q or S suffix)Grades
    • Low-Power Device (L suffix)
  • VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core
    • Eight Highly Independent Functional Units With VelociTI.2 Extensions:
      • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
      • Two Multipliers Support Four 16 × 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 × 8-Bit Multiplies (16-Bit Results) per Clock Cycle
    • Load-Store Architecture With Non-Aligned Support
    • 64 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
    • Additional C64x+™ Enhancements
      • Protected Mode Operation
      • Exceptions Support for Error Detection and Program Redirection
      • Hardware Support for Modulo Loop Auto-Focus Module Operation
  • C64x+ Instruction Set Features
    • Byte-Addressable (8-/16-/32-/64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • VelociTI.2 Increased Orthogonality
    • C64x+ Extensions
      • Compact 16-bit Instructions
      • Additional Instructions to Support Complex Multiplies
  • C64x+ L1/L2 Memory Architecture
    • 256K-Bit (32K-Byte) L1P Program RAM/Cache [Flexible Allocation]
    • 640K-Bit (80K-Byte) L1D Data RAM/Cache [Flexible Allocation]
    • 1M-Bit (128K-Byte) L2 Unified Mapped RAM/Cache [Flexible Allocation]
  • Endianess: Supports Both Little Endian and Big Endian
  • External Memory Interfaces (EMIFs)
    • 32-Bit DDR2 SDRAM Memory Controller With 256M-Byte Address Space (1.8-V I/O)
      • Supports up to 333-MHz (data rate) bus and interfaces to DDR2-400 SDRAM
    • Asynchronous 16-Bit Wide EMIF (EMIFA) With up to 128M-Byte Address Reach
      • Flash Memory Interfaces
        • NOR (8-/16-Bit-Wide Data)
        • NAND (8-/16-Bit-Wide Data)
  • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
  • Two 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
  • One 64-Bit Watch Dog Timer
  • Two UARTs (One with RTS and CTS Flow Control)
  • Master/Slave Inter-Integrated Circuit (I2C Bus™)
  • Two Multichannel Buffered Serial Ports (McBSPs)
    • I2S and TDM
    • AC97 Audio Codec Interface
    • SPI
    • Standard Voice Codec Interface (AIC12)
    • Telecom Interfaces - ST-Bus, H-100
    • 128 Channel Mode
  • Multichannel Audio Serial Port (McASP0)
    • Four Serializers and SPDIF (DIT) Mode
  • 16-Bit Host-Port Interface (HPI)
  • 32-Bit 33-MHz, 3.3-V Peripheral Component Interconnect (PCI) Master/Slave Interface
  • 10/100 Mb/s Ethernet MAC (EMAC)
    • IEEE 802.3 Compliant
    • Supports Multiple Media Independent Interfaces (MII, RMII)
    • Management Data Input/Output (MDIO) Module
  • VLYNQ™ Interface (FPGA Interface)
  • Three Pulse Width Modulator (PWM) Outputs
  • On-Chip ROM Bootloader
  • Individual Power-Savings Modes
  • Flexible PLL Clock Generators
  • IEEE-1149.1 (JTAG™) Boundary-Scan-Compatible
  • Up to 111 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions)
  • Packages:
    • 361-Pin Pb-Free PBGA Package (ZWT Suffix), 0.8-mm Ball Pitch
    • 376-Pin Plastic BGA Package (ZDU Suffix), 1.0-mm Ball Pitch
  • 0.09-µm/6-Level Cu Metal Process (CMOS)
  • 3.3-V and 1.8-V I/O, 1.2-V Internal (-7/-6/-5/-4/-Q6/-Q5/-Q4)
  • 3.3-V and 1.8-V I/O, 1.05-V Internal (-7/-6/-5/-4/-L/-Q5)
  • APPLICATIONS
    • Telecom
    • Audio
    • Industrial Applications
  • Community Reesources

All trademarks are the property of their respective owners.

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Description

The TMS320C64x+™ DSPs (including the TMS320C6424 device) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The C6424 device is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for digital signal processor applications. The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform. The C64x™ DSPs support added functionality and have an expanded instruction set from previous devices.

Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and C64x+ CPU, respectively.

With performance of up to 4800 million instructions per second (MIPS) at a clock rate of 600 MHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units-two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The eight functional units include instructions to accelerate the performance in telecom, audio, and industrial applications. The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. For more details on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732).

The C6424 also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The C6424 core uses a two-level cache-based architecture. The Level 1 program memory/cache (L1P) consists of a 256K-bit memory space that can be configured as mapped memory or direct mapped cache, and the Level 1 data (L1D) consists of a 640K-bit memory space–384K-bit of which is mapped memory and 256K-bit of which can be configured as mapped memory or 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 1M-bit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.

The peripheral set includes: a 10/100 Mb/s Ethernet MAC (EMAC) with a management data input/output (MDIO) module; a 4-bit transmit, 4-bit receive VLYNQ interface; an inter-integrated circuit (I2C) Bus interface; two multichannel buffered serial ports (McBSPs); a multichannel audio serial port (McASP0) with 4 serializers; 2 64-bit general-purpose timers each configurable as 2 independent 32-bit timers; 1 64-bit watchdog timer; a user-configurable 16-bit host-port interface (HPI); up to 111-pins of general-purposeinput/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 2 UARTs with hardware handshaking support on 1 UART; 3 pulse width modulator (PWM) peripherals; 1 peripheral component interconnect (PCI) [33 MHz]; and 2 glueless external memory interfaces: an asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a higher speed synchronous memory interface for DDR2.

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the C6424 and the network. The C6424 EMAC supports 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support.

The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system.

The I2C and VLYNQ ports allow C6424 to easily control peripheral devices and/or communicate with host processors.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.

The C6424 has a complete set of development tools. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

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No design support from TI available

This product does not have ongoing design support from TI for new projects, such as new content or software updates. If available, you will find relevant collateral, software and tools in the product folder. You can also search for archived information in the TI E2ETM support forums.

Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 44
Type Title Date
* Datasheet TMS320C6424 Fixed-Point Digital Signal Processor datasheet (Rev. D) Jan. 11, 2010
* Errata TMS320C6424/21 Digital Signal Processor Silicon Errata (Revs 1.3 1.2 1.1 & 1.0) (Rev. D) Aug. 12, 2011
User guides SYS/BIOS (TI-RTOS Kernel) User's Guide (Rev. V) Jun. 01, 2020
Application notes How to Migrate CCS 3.x Projects to the Latest CCS Feb. 06, 2020
User guides SYS/BIOS (TI-RTOS Kernel) User's Guide (Rev. U) Feb. 07, 2018
Application notes Plastic Ball Grid Array [PBGA] Application Note (Rev. B) Aug. 13, 2015
Application notes Using the TMS320C642x Bootloader (Rev. B) Mar. 23, 2012
Application notes TMS320C642x Power Consumption Summary (Rev. D) Feb. 17, 2012
Application notes Introduction to TMS320C6000 DSP Optimization Oct. 06, 2011
User guides TMS320C642x DSP Inter-Integrated Circuit (I2C) Module User's Guide (Rev. D) Mar. 25, 2011
User guides TMS320C642x DSP DDR2 Memory Controller User's Guide (Rev. B) Jan. 12, 2011
User guides TMS320C642x DSP EMAC/MDIO User's Guide (Rev. C) Dec. 23, 2010
User guides TMS320C642x DSP Pulse-Width Modulator (PWM) User's Guide (Rev. B) Aug. 05, 2010
User guides TMS320C642x DSP 64-Bit Timer User's Guide (Rev. A) Aug. 03, 2010
User guides TMS320C64x+ DSP Megamodule Reference Guide (Rev. K) Aug. 03, 2010
User guides TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (Rev. J) Jul. 30, 2010
User guides TMS320C642x DSP Peripheral Component Interconnect (PCI) User's Guide (Rev. C) May 14, 2010
User guides TMS320C642x DSP Universal Asynchronous Receiver/Transmitter (UART) User's Guide (Rev. C) Dec. 15, 2009
User guides TMS320C642x DSP Asynchronous External Memory Interface (EMIF) User's Guide (Rev. B) Feb. 24, 2009
User guides TMS320C64x+ DSP Cache User's Guide (Rev. B) Feb. 11, 2009
Application notes Implementing DDR2 PCB Layout on the TMS320C6424 DSP Oct. 16, 2008
Application notes 12Vin C642x Power using Integrated-FET DC/DC Converters and LDO Oct. 09, 2008
Application notes 5Vin C642x Power using a PMIC (Multi-output DC/DC Converter) Oct. 09, 2008
Application notes TMS320C620x/C642x McBSP: UART (Rev. C) Sep. 09, 2008
Application notes Migrating from EDMA v2.0 to EDMA v3.0 TMS320C64X DSP (Rev. A) Aug. 21, 2008
Application notes Understanding TI's PCB Routing Rule-Based DDR Timing Specification (Rev. A) Jul. 17, 2008
User guides TMS320C642x DSP Host Port Interface (HPI) User's Guide (Rev. A) Jul. 16, 2008
User guides TMS320C64x+ DSP Image/Video Processing Library (v2.0) Programmer's Reference (Rev. A) May 05, 2008
User guides TMS320C642x DSP General-Purpose Input/Output (GPIO) User's Guide (Rev. A) Mar. 18, 2008
User guides TMS320C642x DSP Multichannel Audio Serial Port (McASP) User's Guide (Rev. C) Mar. 13, 2008
User guides TMS320C64x+ DSP Little-Endian Library Programmer's Reference (Rev. B) Mar. 06, 2008
User guides TMS320C642x DSP Enhanced DMA (EDMA) Controller User's Guide (Rev. A) Mar. 03, 2008
User guides TMS320C642x DSP Power and Sleep Controller (PSC) User's Guide (Rev. A) Feb. 05, 2008
User guides TMS320C642x DSP Phase-Locked Loop Controller (PLLC) User's Guide (Rev. B) Dec. 12, 2007
Application notes Using DMA with Framework Components for C64x+ (Rev. A) Oct. 29, 2007
User guides TMS320C642x DSP VLYNQ Port User's Guide (Rev. B) Sep. 20, 2007
User guides TMS320C642x DSP Multichannel Buffered Serial Port (McBSP) User's Guide (Rev. B) Sep. 17, 2007
Application notes TMS320C642x Pin Multiplexing Utility Jul. 09, 2007
Application notes Thermal Considerations for the DM64xx, DM64x, and C6000 Devices May 20, 2007
User guides TMS320C642x DSP Peripherals Overview Reference Guide Mar. 04, 2007
User guides TMS320C64x+ DSP Big-Endian Library Programmer's Reference Mar. 10, 2006
User guides TMS320C64x+ Image/Video Processing Library Programmer's Reference Mar. 10, 2006
Application notes Migrating from TMS320C64x to TMS320C64x+ (Rev. A) Oct. 20, 2005
User guides Download: C64x+ Benchmarks (v1.00) Jul. 06, 2005

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Software development

DEBUG PROBES Download
XDS200 USB Debug Probe
TMDSEMU200-U The Spectrum Digital XDS200 is the first model of the XDS200 family of debug probes (emulators) for TI processors. The XDS200 family features a balance of low cost with good performance between the super low cost XDS110 and the high performance XDS560v2, while supporting a wide variety of standards (...)
295
Features

The XDS200 is the mid-range family of JTAG debug probes (emulators) for TI processors. Designed to deliver good performance and the most common features that place it between the low cost XDS110 and the high performance XDS560v2, the XDS200 is the balanced solution to debug TI microcontrollers (...)

DEBUG PROBES Download
XDS560v2 System Trace USB Debug Probe
TMDSEMU560V2STM-U The XDS560v2 System Trace is the first model of the XDS560v2 family of high-performance debug probes (emulators) for TI processors. The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).

The (...)

995
Features

XDS560v2 is the latest variant of the XDS560 family of high-performance debug probes (emulators) for TI processors. With the fastest speeds and most features of the entire XDS family, XDS560v2 is the most comprehensive solution to debug TI microcontrollers, processors and wireless connectivity (...)

DEBUG PROBES Download
XDS560v2 System Trace USB & Ethernet Debug Probe
TMDSEMU560V2STM-UE The XDS560v2 System Trace is the first model of the XDS560v2 family of high-performance debug probes (emulators) for TI processors. The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).

The (...)

1495
Features
  • XDS560v2 is the latest variant of the XDS560 family of high-performance debug probes (emulators) for TI processors. With the fastest speeds and most features of the entire XDS family, XDS560v2 is the most comprehensive solution to debug TI microcontrollers, processors and wireless connectivity (...)

DRIVERS & LIBRARIES Download
TI-RTOS Networking
NDKTCPIP TI-RTOS Networking (formerly known as the NDK or Network Developers Kit) combines dual mode IPv4/IPv6 stack with some network applications. TI-RTOS Networking support is available for both Ethernet-enabled MCUs as a part of TI-RTOS and also for TMS320C6000(TM) High Performance DSP-based devices. 
Features

TI-RTOS Networking includes:

  • Core TCP/IP protocol stack: Dual-mode IPv6/IPv4 stack in both source and binary only including VLAN packet priority marking, TCP, UDP, ICMP, IGMP, IP, and ARP
  • Network applications: HTTP, TELNET, TFTP, DNS, DHCP (IPv4 only) in both source and binary form
  • Serial support: PPP (...)
DRIVERS & LIBRARIES Download
C62x/C64x Fast Run-Time Support (RTS) Library
SPRC122 The C62x/64x FastRTS Library is an optimized, floating-point function library for C programmers using either TMS320C62x or TMS320C64x devices. These routines are typically used in computationally intensive real-time applications where optimal execution speed is critical. By replacing the current (...)
DRIVERS & LIBRARIES Download
TMS320C5000/6000 Image Library (IMGLIB)
SPRC264 C5000/6000 Image Processing Library (IMGLIB) is an optimized image/video processing function library for C programmers. It includes C-callable general-purpose image/video processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
Features

Image Analysis

  • Image boundry and perimeter
  • Morphological operation
  • Edge detection
  • Image Histogram
  • Image thresholding

Image filtering and format conversion

  • Color space conversion
  • Image convolution
  • Image correlation
  • Error diffusion
  • Median filtering
  • Pixel expansion

Image compression and decompression

  • Forward and (...)
DRIVERS & LIBRARIES Download
TMS320C6000 DSP Library (DSPLIB)
SPRC265 TMS320C6000 Digital Signal Processor Library (DSPLIB) is a platform-optimized DSP function library for C programmers. It includes C-callable, general-purpose signal-processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
Features

Optimized DSP routines including functions for:

  • Adaptive filtering
  • Correlation
  • FFT
  • Filtering and convolution: FIR, biquad, IIR, convolution
  • Math: Dot products, max value, min value, etc.
  • Matrix operations
DRIVERS & LIBRARIES Download
Telecom and Media Libraries - FAXLIB, VoLIB and AEC/AER for TMS320C64x+ and TMS320C55x Processors
TELECOMLIB Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be acquired (...)
Features

VoLIB

  • Telogy Software Line Echo Canceller (ECU)
  • Tone Detection Unit (TDU)
  • Caller ID Detection/Generation (CID)
  • Tone Generation Unit (TGU)
  • Voice Activity Detection Unit (VAU)
  • Noise Matching Functions
  • Packet Loss Concealment (PLC)
  • Voice Enhancement Unit (VEU)  

FAXLIB

  • Fax Interface Unit (FIU)
  • Fax Modem (FM)
  • (...)
IDES, CONFIGURATION, COMPILERS & DEBUGGERS Download
C6000 code generation tools - compiler
C6000-CGT — The TI C6000 C/C++ Compiler and Assembly Language Tools support development of applications for TI C6000 Digital Signal Processor platforms, including the C66x multi-core, C674x and C64x+ single-core Digital Signal Processors.
Features
  • Available in C6000 Code Generation Tools starting with v8.3.0:
    • Supports the C++14 Standard ISO/IEC 14882:2014 (C++03 is no longer supported)
  • Available in C6000 Code Generation Tools starting with release v8.2.0:
    • Conversion of floating-point values to unsigned char or short no longer generate RTS (...)

Design tools & simulation

SIMULATION MODELS Download
SPRM240C.ZIP (267 KB) - IBIS Model
SIMULATION MODELS Download
SPRM241B.ZIP (267 KB) - IBIS Model
SIMULATION MODELS Download
SPRM250A.ZIP (10 KB) - BSDL Model
SIMULATION MODELS Download
SPRM251A.ZIP (10 KB) - BSDL Model

CAD/CAE symbols

Package Pins Download
BGA (ZDU) 376 View options
NFBGA (ZWT) 361 View options

Ordering & quality

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