Product details

Operating system Integrity, Linux, Neutrino, PrOS, Windows Embedded CE Rating Catalog Operating temperature range (C) 0 to 85
Operating system Integrity, Linux, Neutrino, PrOS, Windows Embedded CE Rating Catalog Operating temperature range (C) 0 to 85
NFBGA (ZCE) 337 169 mm² 13 x 13
  • Highlights
    • High-Performance Digital Media System-On-Chip (DMSoC)
    • Up to 216-MHz ARM926EJ-STM Clock Rate
    • Digital HDTV (720p/1080i) output for connection to external encoder
    • Video Processing Subsystem
      • Hardware IPIPE for Real-Time Image Processing
      • Up to 14-bit CCD/CMOS Digital Interface
      • Histogram Module
      • Resize Image 1/16x to 8x
      • Hardware On-Screen Display
      • Up to 75-MHz Pixel Clock
      • Composite NTSC/PAL video encoder output
    • Peripherals include DDR and mDDR SDRAM, 2 MMC/SD/SDIO and SmartMedia Flash Card Interfaces, USB 2.0, 3 UARTs and 3 SPIs
    • Enhanced Direct-Memory-Access (EDMA)
    • Configurable Power-Saving Modes
    • On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash, MMC/SD, or UART
    • 3.3-V and 1.8-V I/O, 1.3-V Core
    • Debug Interface Support
    • Up to 104 General-Purpose I/O (GPIO) Pins
    • 337-Pin Ball Grid Array at 65 nm Process Technology
  • High-Performance Digital Media System-on-Chip
    • 135-, 216-MHz ARM926EJ-S™ Clock Rate
    • Fully Software-Compatible With ARM™
    • Extended Temperature 135- and 216-MHz Devices are Available
  • ARM926EJ-S Core
    • Support for 32-Bit and 16-Bit (Thumb Mode) Instruction Sets
    • DSP Instruction Extensions and Single Cycle MAC
    • ARM® Jazelle® Technology
    • EmbeddedICE-RT™ Logic for Real-Time Debug
  • ARM9 Memory Architecture
    • 16K-Byte Instruction Cache
    • 8K-Byte Data Cache
    • 32K-Byte RAM
    • 8K-Byte ROM
    • Little Endian
  • Video Processing Subsystem
    • Front End Provides:
      • Hardware IPIPE for Real-Time Image Processing
      • Up to 14-bit CCD/CMOS Digital Interface
      • 16-/8-bit Generic YcBcR-4:2 Interface (BT.601)
      • 10-/8-bit CCIR6565/BT655 Interface
      • Up to 75-MHz Pixel Clock
      • Histogram Module
      • Resize Engine
        • Resize Images From 1/16x to 8x
        • Separate Horizontal/Vertical Control
        • Two Simultaneous Output Paths
    • Back End Provides:
      • Hardware On-Screen Display (OSD)
      • Composite NTSC/PAL video encoder output
      • 8-/16-bit YCC and Up to 18-Bit RGB666 Digital Output
      • BT.601/BT.656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface
      • Digital HDTV (720p/1080i)output for connection to external encoder
  • External Memory Interfaces (EMIFs)
    • DDR2 and mDDR SDRAM 16-bit wide EMIF With 256 MByte Address Space (1.8-V I/O)
    • Asynchronous16-/8-bit Wide EMIF (AEMIF)
      • Flash Memory Interfaces
        • NAND (8-/16-bit Wide Data)
        • OneNAND(16-bit Wide Data)
  • Flash Card Interfaces
    • Two Multimedia Card (MMC) / Secure Digital (SD/SDIO)
    • SmartMedia
  • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
  • USB Port with Integrated 2.0 High-Speed PHY that Supports
    • USB 2.0 Full and High-Speed Device
    • USB 2.0 Low, Full, and High-Speed Host
  • Three 64-Bit General-Purpose Timers (each configurable as two 32-bit timers)
  • One 64-Bit Watch Dog Timer
  • Three UARTs (One fast UART with RTS and CTS Flow Control)
  • Three Serial Port Interfaces (SPI) each with two Chip-Selects
  • One Master/Slave Inter-Integrated Circuit (I2C) Bus®
  • Two Audio Serial Port (ASP)
    • I2S and TDM I2S
    • AC97 Audio Codec Interface
    • S/PDIF via Software
    • Standard Voice Codec Interface (AIC12)
    • SPI Protocol (Master Mode Only)
  • Four Pulse Width Modulator (PWM) Outputs
  • Four RTO (Real Time Out) Outputs
  • Up to 104 General-Purpose I/O (GPIO) Pins (Multiplexed with Other Device Functions)
  • On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash, MMC/SD, or UART
  • Configurable Power-Saving Modes
  • Crystal or External Clock Input (typically 24 MHz or 36 MHz)
  • Flexible PLL Clock Generators
  • Debug Interface Support
    • IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
    • ETB™ (Embedded Trace Buffer™) with4K-Bytes Trace Buffer memory
    • Device Revision ID Readable by ARM
  • 337-Pin Ball Grid Array (BGA) Package (ZCE Suffix), 0.65-mm Ball Pitch
  • 90nm Process Technology
  • 3.3-V and 1.8-V I/O, 1.3-V Internal
  • Community Resources

Windows is a trademark of Microsoft.
All other trademarks are the property of their respective owners.

  • Highlights
    • High-Performance Digital Media System-On-Chip (DMSoC)
    • Up to 216-MHz ARM926EJ-STM Clock Rate
    • Digital HDTV (720p/1080i) output for connection to external encoder
    • Video Processing Subsystem
      • Hardware IPIPE for Real-Time Image Processing
      • Up to 14-bit CCD/CMOS Digital Interface
      • Histogram Module
      • Resize Image 1/16x to 8x
      • Hardware On-Screen Display
      • Up to 75-MHz Pixel Clock
      • Composite NTSC/PAL video encoder output
    • Peripherals include DDR and mDDR SDRAM, 2 MMC/SD/SDIO and SmartMedia Flash Card Interfaces, USB 2.0, 3 UARTs and 3 SPIs
    • Enhanced Direct-Memory-Access (EDMA)
    • Configurable Power-Saving Modes
    • On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash, MMC/SD, or UART
    • 3.3-V and 1.8-V I/O, 1.3-V Core
    • Debug Interface Support
    • Up to 104 General-Purpose I/O (GPIO) Pins
    • 337-Pin Ball Grid Array at 65 nm Process Technology
  • High-Performance Digital Media System-on-Chip
    • 135-, 216-MHz ARM926EJ-S™ Clock Rate
    • Fully Software-Compatible With ARM™
    • Extended Temperature 135- and 216-MHz Devices are Available
  • ARM926EJ-S Core
    • Support for 32-Bit and 16-Bit (Thumb Mode) Instruction Sets
    • DSP Instruction Extensions and Single Cycle MAC
    • ARM® Jazelle® Technology
    • EmbeddedICE-RT™ Logic for Real-Time Debug
  • ARM9 Memory Architecture
    • 16K-Byte Instruction Cache
    • 8K-Byte Data Cache
    • 32K-Byte RAM
    • 8K-Byte ROM
    • Little Endian
  • Video Processing Subsystem
    • Front End Provides:
      • Hardware IPIPE for Real-Time Image Processing
      • Up to 14-bit CCD/CMOS Digital Interface
      • 16-/8-bit Generic YcBcR-4:2 Interface (BT.601)
      • 10-/8-bit CCIR6565/BT655 Interface
      • Up to 75-MHz Pixel Clock
      • Histogram Module
      • Resize Engine
        • Resize Images From 1/16x to 8x
        • Separate Horizontal/Vertical Control
        • Two Simultaneous Output Paths
    • Back End Provides:
      • Hardware On-Screen Display (OSD)
      • Composite NTSC/PAL video encoder output
      • 8-/16-bit YCC and Up to 18-Bit RGB666 Digital Output
      • BT.601/BT.656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface
      • Digital HDTV (720p/1080i)output for connection to external encoder
  • External Memory Interfaces (EMIFs)
    • DDR2 and mDDR SDRAM 16-bit wide EMIF With 256 MByte Address Space (1.8-V I/O)
    • Asynchronous16-/8-bit Wide EMIF (AEMIF)
      • Flash Memory Interfaces
        • NAND (8-/16-bit Wide Data)
        • OneNAND(16-bit Wide Data)
  • Flash Card Interfaces
    • Two Multimedia Card (MMC) / Secure Digital (SD/SDIO)
    • SmartMedia
  • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
  • USB Port with Integrated 2.0 High-Speed PHY that Supports
    • USB 2.0 Full and High-Speed Device
    • USB 2.0 Low, Full, and High-Speed Host
  • Three 64-Bit General-Purpose Timers (each configurable as two 32-bit timers)
  • One 64-Bit Watch Dog Timer
  • Three UARTs (One fast UART with RTS and CTS Flow Control)
  • Three Serial Port Interfaces (SPI) each with two Chip-Selects
  • One Master/Slave Inter-Integrated Circuit (I2C) Bus®
  • Two Audio Serial Port (ASP)
    • I2S and TDM I2S
    • AC97 Audio Codec Interface
    • S/PDIF via Software
    • Standard Voice Codec Interface (AIC12)
    • SPI Protocol (Master Mode Only)
  • Four Pulse Width Modulator (PWM) Outputs
  • Four RTO (Real Time Out) Outputs
  • Up to 104 General-Purpose I/O (GPIO) Pins (Multiplexed with Other Device Functions)
  • On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash, MMC/SD, or UART
  • Configurable Power-Saving Modes
  • Crystal or External Clock Input (typically 24 MHz or 36 MHz)
  • Flexible PLL Clock Generators
  • Debug Interface Support
    • IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
    • ETB™ (Embedded Trace Buffer™) with4K-Bytes Trace Buffer memory
    • Device Revision ID Readable by ARM
  • 337-Pin Ball Grid Array (BGA) Package (ZCE Suffix), 0.65-mm Ball Pitch
  • 90nm Process Technology
  • 3.3-V and 1.8-V I/O, 1.3-V Internal
  • Community Resources

Windows is a trademark of Microsoft.
All other trademarks are the property of their respective owners.

The DM335 processor is a low-cost, low-power processor providing advanced graphical user interface for display applications that do not require video compression and decompression. Coupled with a video processing subsystem (VPSS) that provides 720p display, the DM335 processor is powered by a 135/216-MHz ARM926EJ-S core so developers can create feature-rich graphical user interfaces allowing customers to interact with their portable, electronic devices such as video-enabled universal remote controls, Internet radio, e-books, video doorbells, and digital telescopes. The new DM335 is packed with the same peripherals as its predecessor, the TMS320DM355 device, including high-speed USB 2.0 on-the-go, external memory interface (EMIF), mobile DDR/DDR2, two SDIO ports, three UART Ports, two Audio Serial Ports, three SPI Ports, and SLC/MCL NAND Flash memory support. These peripherals help customers create DM335 processor-based designs that add video and audio excitement to a wide range of today's static user-interface applications while keeping silicon costs and power consumption low. The new digital media processor is completely scalable with the DM355 processor and Digital Video Evaluation Board (DVEVM), allowing customers to utilize their same code for their new DM335 processor focused designs.

The new DM335 device delivers a sophisticated suite of capabilities allowing for flexible image capture and display. Through its user interface technology, such as a four-level on-screen display, developers are able to create picture-within-picture and video-within-video as well as innovative graphic user interfaces. This is especially important for portable products that require the use of button or touch screen, such as portable karaoke, video surveillance and electronic gaming applications. Additional advanced capture and imaging technologies include support for CCD/CMOS image sensors, resize capability and video stabilization. The 1280-by-960-pixel digital LCD connection runs on a 75-MHz pixel clock and supports TV composite output for increased expandability. This highly integrated device is packaged in a 13 x 13 mm, 337 pin , 0.65 mm pitch BGA package.

The DM335 processor core is an ARM926EJ-S RISC processor. The ARM926EJ-S is a 32-bit processor core that performs 32-bit and 16-bit instructions and processes 32-bit, 16-bit, and 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously. The ARM core incorporates:

  • A coprocessor 15 (CP15) and protection module
  • Data and program Memory Management Units (MMUs) with table look-aside buffers.
  • Separate 16K-byte instruction and 8K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT).

The DM335 device has a Video Processing Subsystem (VPSS) with two configurable video/imaging peripherals:

  • A Video Processing Front-End (VPFE)
  • A Video Processing Back-End (VPBE)

The VPFE port provides an interface for CCD/CMOS imager modules and video decoders. The VPBE provides hardware On Screen Display (OSD) support and composite NTSC/PAL and digital LCD output.

The DM335 peripheral set includes:

  • An inter-integrated circuit (I2C) Bus interface
  • Two audio serial ports (ASP)
  • Three 64-bit general-purpose timers each configurable as two independent 32-bit timers
  • A 64-bit watchdog timer
  • Up to 104-pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals
  • Three UARTs with hardware handshaking support on one UART
  • Three serial port Interfaces (SPI)
  • Four pulse width modulator (PWM) peripherals
  • Four real time out (RTO) outputs
  • Two Multi-Media Card / Secure Digital (MMC/SD/SDIO) interfaces
  • Wireless interfaces (Bluetooth, WLAN, WUSB) through SDIO
  • A USB 2.0 full and high-speed device and host interface
  • Two external memory interfaces:
    • An asynchronous external memory interface (AEMIF) for slower memories/peripherals such as NAND and OneNAND,
    • A high speed synchronous memory interface for DDR2/mDDR.

For software development support the DM335 has a complete set of ARM development tools which include: C compilers, assembly optimizers to simplify programming and scheduling, and a Windows™debugger interface for visibility into source code execution.

The DM335 processor is a low-cost, low-power processor providing advanced graphical user interface for display applications that do not require video compression and decompression. Coupled with a video processing subsystem (VPSS) that provides 720p display, the DM335 processor is powered by a 135/216-MHz ARM926EJ-S core so developers can create feature-rich graphical user interfaces allowing customers to interact with their portable, electronic devices such as video-enabled universal remote controls, Internet radio, e-books, video doorbells, and digital telescopes. The new DM335 is packed with the same peripherals as its predecessor, the TMS320DM355 device, including high-speed USB 2.0 on-the-go, external memory interface (EMIF), mobile DDR/DDR2, two SDIO ports, three UART Ports, two Audio Serial Ports, three SPI Ports, and SLC/MCL NAND Flash memory support. These peripherals help customers create DM335 processor-based designs that add video and audio excitement to a wide range of today's static user-interface applications while keeping silicon costs and power consumption low. The new digital media processor is completely scalable with the DM355 processor and Digital Video Evaluation Board (DVEVM), allowing customers to utilize their same code for their new DM335 processor focused designs.

The new DM335 device delivers a sophisticated suite of capabilities allowing for flexible image capture and display. Through its user interface technology, such as a four-level on-screen display, developers are able to create picture-within-picture and video-within-video as well as innovative graphic user interfaces. This is especially important for portable products that require the use of button or touch screen, such as portable karaoke, video surveillance and electronic gaming applications. Additional advanced capture and imaging technologies include support for CCD/CMOS image sensors, resize capability and video stabilization. The 1280-by-960-pixel digital LCD connection runs on a 75-MHz pixel clock and supports TV composite output for increased expandability. This highly integrated device is packaged in a 13 x 13 mm, 337 pin , 0.65 mm pitch BGA package.

The DM335 processor core is an ARM926EJ-S RISC processor. The ARM926EJ-S is a 32-bit processor core that performs 32-bit and 16-bit instructions and processes 32-bit, 16-bit, and 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously. The ARM core incorporates:

  • A coprocessor 15 (CP15) and protection module
  • Data and program Memory Management Units (MMUs) with table look-aside buffers.
  • Separate 16K-byte instruction and 8K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT).

The DM335 device has a Video Processing Subsystem (VPSS) with two configurable video/imaging peripherals:

  • A Video Processing Front-End (VPFE)
  • A Video Processing Back-End (VPBE)

The VPFE port provides an interface for CCD/CMOS imager modules and video decoders. The VPBE provides hardware On Screen Display (OSD) support and composite NTSC/PAL and digital LCD output.

The DM335 peripheral set includes:

  • An inter-integrated circuit (I2C) Bus interface
  • Two audio serial ports (ASP)
  • Three 64-bit general-purpose timers each configurable as two independent 32-bit timers
  • A 64-bit watchdog timer
  • Up to 104-pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals
  • Three UARTs with hardware handshaking support on one UART
  • Three serial port Interfaces (SPI)
  • Four pulse width modulator (PWM) peripherals
  • Four real time out (RTO) outputs
  • Two Multi-Media Card / Secure Digital (MMC/SD/SDIO) interfaces
  • Wireless interfaces (Bluetooth, WLAN, WUSB) through SDIO
  • A USB 2.0 full and high-speed device and host interface
  • Two external memory interfaces:
    • An asynchronous external memory interface (AEMIF) for slower memories/peripherals such as NAND and OneNAND,
    • A high speed synchronous memory interface for DDR2/mDDR.

For software development support the DM335 has a complete set of ARM development tools which include: C compilers, assembly optimizers to simplify programming and scheduling, and a Windows™debugger interface for visibility into source code execution.

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This product does not have ongoing design support from TI for new projects, such as new content or software updates. If available, you will find relevant collateral, software and tools in the product folder. You can also search for archived information in the TI E2ETM support forums.

Technical documentation

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Type Title Date
* Data sheet TMS320DM335 Digital Media System-on-Chip (DMSoC) datasheet (Rev. C) 24 Jun 2010
* Errata TMS320DM335 Digital Media System-on-Chip Silicon Erata (Revs 1.1, 1.3 and 1.4) (Rev. B) 24 Jan 2010
Technical article Bringing the next evolution of machine learning to the edge 27 Nov 2018
Application note High-Speed Interface Layout Guidelines (Rev. H) 11 Oct 2018
Technical article How quality assurance on the Processor SDK can improve software scalability 22 Aug 2018
Technical article Clove: Low-Power video solutions based on Sitara™ AM57x processors 21 Jul 2016
Technical article TI's new DSP Benchmark Site 08 Feb 2016
Application note Powering the TMS320DM335 and TMS320DM355 with the TPS650061 13 Oct 2011
Application note Migrating From TMS320DM355/335 Silicon Revision 1.1 to 1.3 or 1.4 (Rev. B) 05 Jan 2011
User guide TMS320DM335 DMSoC Pulse-Width Modulator User's Guide (Rev. A) 25 Aug 2010
User guide TMS320DM335 DMSoC ARM Subsystem Reference Guide (Rev. A) 15 Jul 2010
More literature TMS320DM3x DaVinci Video Processors 11 Apr 2010
Application note Implementing DDR2/mDDR PCB Layout on the TMS320DM335 DMSoC (Rev. D) 11 Nov 2009
More literature TMS320DM3x Highlights 03 Mar 2009
More literature Complimentary Analog Devices for the DM335 Digital Media Processor 17 Feb 2009
User guide TMS320DM335 DMSoC Video Processing Back-End User's Guide (Rev. A) 24 Oct 2008
More literature DaVinci Technology Overview Brochure (Rev. B) 27 Sep 2008
Application note Migrating from EDMA v2.0 to EDMA v3.0 TMS320C64X DSP (Rev. A) 21 Aug 2008
Application note TMS320DM355 DSP Power Reference Design PR742 (Rev. A) 08 Aug 2008
Application note Understanding TI's PCB Routing Rule-Based DDR Timing Specification (Rev. A) 17 Jul 2008
User guide TMS320DM335 DMSoC Asynchronous External Memory Interface(EMIF) 15 Jul 2008
User guide TMS320DM335 DMSoC Audio Serial Port 15 Jul 2008
User guide TMS320DM335 DMSoC DDR2/mDDR Memory Controller Reference Guide 15 Jul 2008
User guide TMS320DM335 DMSoC Enhanced Direct Memory Access (EDMA) Controller User's Guide 15 Jul 2008
User guide TMS320DM335 DMSoC General-Purpose Input/Output (GPIO) User's Guide 15 Jul 2008
User guide TMS320DM335 DMSoC Inter-Integrated Circuit (I2C) 15 Jul 2008
User guide TMS320DM335 DMSoC MMC/SD Reference Guide 15 Jul 2008
User guide TMS320DM335 DMSoC Peripheral Overview Reference Guide 15 Jul 2008
User guide TMS320DM335 DMSoC Real Time Out (RTO) User's Guide 15 Jul 2008
User guide TMS320DM335 DMSoC Serial Peripheral Interface (SPI) 15 Jul 2008
User guide TMS320DM335 DMSoC Timer/Watchdog Timer User's Guide 15 Jul 2008
User guide TMS320DM335 DMSoC Universal Asynchronous Receiver/Transmitter (UART) 15 Jul 2008
User guide TMS320DM335 DMSoC Universal Serial Bus (USB) User's Guide 15 Jul 2008
User guide TMS320DM335 DMSoC Video Processing Front-End User's Guide 15 Jul 2008
Application note Building a Small Embedded Linux Kernel Example (Rev. A) 27 May 2008

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Debug probe

TMDSEMU200-U — XDS200 USB Debug Probe

The XDS200 is a debug probe (emulator) used for debugging TI embedded devices.  The XDS200 features a balance of low cost with good performance as compared to the low cost XDS110 and the high performance XDS560v2.  It supports a wide variety of standards (IEEE1149.1, IEEE1149.7, SWD) in a (...)

In stock
Limit: 3
Debug probe

TMDSEMU560V2STM-U — XDS560v2 System Trace USB Debug Probe

The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).  Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors that (...)

In stock
Limit: 1
Debug probe

TMDSEMU560V2STM-UE — XDS560v2 System Trace USB & Ethernet Debug Probe

The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors that (...)

In stock
Limit: 1
Software development kit (SDK)

LINUXDVSDK-DV — Linux Digital Video Software Development Kits (DVSDK) v2x/v3x - DaVinci Digital Media Processors

Effective Oct 2010 - Linux DVSDK v4 has been released. For DaVinci™ devices not listed above, search TI.com for your device part number; This product page will have a link to your current DVSDK.

The Linux™ Digital Video Software Development Kits (DVSDKs) enable DaVinci system integrators to (...)

Application software & framework

TMDMFP — Multimedia Framework Products (MFP) - Codec Engine, Framework Components and XDAIS

Multimedia Framework Products (MFP)

A major advantage of programmable signal processors over fixed-function devices is their ability to accelerate multiple multimedia functions and provide flexible environments to enable user customization. However, sharing scarce embedded hardware resources between (...)

Simulation model

DM335 ZCE IBIS Model (Rev. A)

SPRM317A.ZIP (234 KB) - IBIS Model
Simulation model

DM335 ZCE BSDL Model

SPRM318.ZIP (8 KB) - BSDL Model
Design tool

PROCESSORS-3P-SEARCH — Arm-based MPU, arm-based MCU and DSP third-party search tool

TI has partnered with companies to offer a wide range of software, tools, and SOMs using TI processors to accelerate your path to production. Download this search tool to quickly browse our third-party solutions and find the right third-party to meet your needs. The software, tools and modules (...)
Reference designs

PR2047 — Powering the TMS320DM335 and TMS320DM355 with the TPS650061

Low cost integrated power solution for TI - DM335/355 processors
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NFBGA (ZCE) 337 View options

Ordering & quality

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  • Qualification summary
  • Ongoing reliability monitoring

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

Support & training

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