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TPIC6259

ACTIVE

8-bit addressable latch with 250mA/ch

Product details

Number of channels 8 Topology Open drain Rating Automotive Operating temperature range (°C) -40 to 125 Vin (min) (V) 4.5 Vin (max) (V) 5.5 Vout (max) (V) 45 Features Enable/Shutdown, Thermal shutdown
Number of channels 8 Topology Open drain Rating Automotive Operating temperature range (°C) -40 to 125 Vin (min) (V) 4.5 Vin (max) (V) 5.5 Vout (max) (V) 45 Features Enable/Shutdown, Thermal shutdown
PDIP (N) 20 228.702 mm² 24.33 x 9.4 SOIC (DW) 20 131.84 mm² 12.8 x 10.3
  • Low rDS(on) . . . 1.3 Typical
  • Avalanche Energy . . . 75 mJ
  • Eight Power DMOS Transistor Outputs of 250-mA
    Continuous Current
  • 1.5-A Pulsed Current Per Output
  • Output Clamp Voltage at 45 V
  • Four Distinct Function Modes
  • Low Power Consumption

  • Low rDS(on) . . . 1.3 Typical
  • Avalanche Energy . . . 75 mJ
  • Eight Power DMOS Transistor Outputs of 250-mA
    Continuous Current
  • 1.5-A Pulsed Current Per Output
  • Output Clamp Voltage at 45 V
  • Four Distinct Function Modes
  • Low Power Consumption

This power logic 8-bit addressable latch controls open-drain DMOS transistor outputs and is designed for general-purpose storage applications in digital systems. Specific uses include working registers, serial-holding registers, and decoders or demultiplexers. This is a multi-functional device capable of storing single-line data in eight addressable latches with 3-to-8 decoding or demultiplexing mode active-low DMOS outputs.

Four distinct modes of operation are selectable by controlling the clear (CLR\) and enable (G\) inputs as enumerated in the function table. In the addressable-latch mode, data at the data-in (D) terminal is written into the addressed latch. The addressed DMOS transistor output inverts the data input with all unaddressed DMOS-transistor outputs remaining in their previous states. In the memory mode, all DMOS-transistor outputs remain in their previous states and are unaffected by the data or address inputs. To eliminate the possibility of entering erroneous data in the latch, enable G\ should be held high (inactive) while the address lines are changing. In the 3-to-8 decoding or demultiplexing mode, the addressed output is inverted with respect to the D input and all other outputs are high. In the clear mode, all outputs are high and unaffected by the address and data inputs.

Separate power and logic level ground pins are provided to facilitate maximum system flexibility. Pins 1, 10, 11, and 20 are internally connected, and each pin must be externally connected to the power system ground in order to minimize parasitic inductance. A single-point connection between pin 9, logic ground (LGND), and pins 1, 10, 11, and 20, power ground (PGND) must be externally made in a manner that reduces crosstalk between the logic and load circuits.

The TPIC6259 is characterized for operation over the operating case temperature range of -40°C to 125°C.

This power logic 8-bit addressable latch controls open-drain DMOS transistor outputs and is designed for general-purpose storage applications in digital systems. Specific uses include working registers, serial-holding registers, and decoders or demultiplexers. This is a multi-functional device capable of storing single-line data in eight addressable latches with 3-to-8 decoding or demultiplexing mode active-low DMOS outputs.

Four distinct modes of operation are selectable by controlling the clear (CLR\) and enable (G\) inputs as enumerated in the function table. In the addressable-latch mode, data at the data-in (D) terminal is written into the addressed latch. The addressed DMOS transistor output inverts the data input with all unaddressed DMOS-transistor outputs remaining in their previous states. In the memory mode, all DMOS-transistor outputs remain in their previous states and are unaffected by the data or address inputs. To eliminate the possibility of entering erroneous data in the latch, enable G\ should be held high (inactive) while the address lines are changing. In the 3-to-8 decoding or demultiplexing mode, the addressed output is inverted with respect to the D input and all other outputs are high. In the clear mode, all outputs are high and unaffected by the address and data inputs.

Separate power and logic level ground pins are provided to facilitate maximum system flexibility. Pins 1, 10, 11, and 20 are internally connected, and each pin must be externally connected to the power system ground in order to minimize parasitic inductance. A single-point connection between pin 9, logic ground (LGND), and pins 1, 10, 11, and 20, power ground (PGND) must be externally made in a manner that reduces crosstalk between the logic and load circuits.

The TPIC6259 is characterized for operation over the operating case temperature range of -40°C to 125°C.

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* Data sheet Power Logic 8-Bit Addressable Latch datasheet (Rev. A) 01 Sep 1995

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PDIP (N) 20 View options
SOIC (DW) 20 View options

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