Product details

Number of supplies monitored 1 Threshold voltage 1 (Typ) (V) 2.93, 4.55 Features Manual reset capable, Watchdog timer Reset threshold accuracy (%) 2.4 Output driver type/reset output Active-low, Push-pull Time delay (ms) 25 Rating Catalog Watchdog timer WDI (sec) 0.2 Operating temperature range (C) -40 to 85
Number of supplies monitored 1 Threshold voltage 1 (Typ) (V) 2.93, 4.55 Features Manual reset capable, Watchdog timer Reset threshold accuracy (%) 2.4 Output driver type/reset output Active-low, Push-pull Time delay (ms) 25 Rating Catalog Watchdog timer WDI (sec) 0.2 Operating temperature range (C) -40 to 85
SOT-23 (DBV) 5 5 mm² 2.9 x 1.6
  • Power-On reset generator with fixed delay time of 200 ms (TPS3823/4/5/8) or 25 ms (TPS3820)
  • Manual reset input (TPS3820/3/5/8)
  • Reset output available in active-low (TPS3820/3/4/5), active-high (TPS3824/5), and open drain (TPS3828)
  • Supply voltage supervision range:
    2.5 V, 3 V, 3.3 V, 5 V
  • Watchdog timer (TPS3820/3/4/8)
  • Supply current of 15 µA (Typical)
  • 5-Pin SOT-23 package
  • Temperature range: −40°C to 85°C (−40°C to 125°C for TPS3823A-33)
  • Power-On reset generator with fixed delay time of 200 ms (TPS3823/4/5/8) or 25 ms (TPS3820)
  • Manual reset input (TPS3820/3/5/8)
  • Reset output available in active-low (TPS3820/3/4/5), active-high (TPS3824/5), and open drain (TPS3828)
  • Supply voltage supervision range:
    2.5 V, 3 V, 3.3 V, 5 V
  • Watchdog timer (TPS3820/3/4/8)
  • Supply current of 15 µA (Typical)
  • 5-Pin SOT-23 package
  • Temperature range: −40°C to 85°C (−40°C to 125°C for TPS3823A-33)

The TPS382x family of supervisors provide circuit initialization and timing supervision, primarily for DSP and processor-based systems. During power on, RESET asserts when the supply voltage VDD becomes greater than 1.1 V. Thereafter, the supply voltage supervisor monitors VDD and keeps RESET active low as long as VDD remains less than the threshold voltage, VIT−. An internal timer delays the return of the output to the inactive state (high) to ensure proper system reset. The delay time, td, starts after VDD has risen above the threshold voltage (VIT− + VHYS). When the supply voltage drops below the threshold voltage VIT−, the output becomes active (low) again. No external components are required. All the devices of this family have a fixed-sense threshold voltage, VIT–, set by an internal voltage divider. The TPS382x family also offers watchdog time out options of 200 ms (TPS3820) and 1.6 s (TPS3823/4/8).

The TPS382x family of supervisors provide circuit initialization and timing supervision, primarily for DSP and processor-based systems. During power on, RESET asserts when the supply voltage VDD becomes greater than 1.1 V. Thereafter, the supply voltage supervisor monitors VDD and keeps RESET active low as long as VDD remains less than the threshold voltage, VIT−. An internal timer delays the return of the output to the inactive state (high) to ensure proper system reset. The delay time, td, starts after VDD has risen above the threshold voltage (VIT− + VHYS). When the supply voltage drops below the threshold voltage VIT−, the output becomes active (low) again. No external components are required. All the devices of this family have a fixed-sense threshold voltage, VIT–, set by an internal voltage divider. The TPS382x family also offers watchdog time out options of 200 ms (TPS3820) and 1.6 s (TPS3823/4/8).

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Technical documentation

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Type Title Date
* Data sheet TPS382x Voltage Monitor With Watchdog Timer datasheet (Rev. M) 23 Jul 2020
Technical article 3 quiescent-current (Iq) specifications you need to understand 12 Nov 2021
Application note Voltage Supervisors (Reset ICs): Frequently Asked Questions (FAQs) (Rev. A) 17 Mar 2020
Selection guide Voltage Supervisors (Reset ICs) Quick Reference Guide (Rev. H) 28 Feb 2020
E-book Voltage Supervisor and Reset ICs: Tips, Tricks and Basics 28 Jun 2019
Application note Latching a Voltage Supervisor (Reset IC) (Rev. A) 05 Apr 2019
Selection guide Power Management Guide 2018 (Rev. R) 25 Jun 2018
Application note Disabling the Watchdog Timer for TI's Family of Supervisors 30 Oct 2003

Design & development

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Evaluation board

TPS382-Q1EVM — Evaluation module for the TPS382x-Q1 voltage supervisors with integrated watchdog

The TPS382-Q1EVM evaluation module (EVM) has five different TPS382x-Q1 devices to let you evaluate and test the different features of the product family.  The EVM includes devices with 2.5-V, 3-V, 3.3-V and 5-V fixed monitoring, watchdog input, manual reset, (...)
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PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Reference designs

TIDA-00929 — Spectrum Analyzer Signal Conditioning and Processing for Capturing Arc Signatures Reference Design

This reference design demonstrates bandwidth-optimized analog front end (AFE) and real-time FIR implementation using low power to capture broadband frequency spectrum in any waveform. An operational amplifier in each signal path is chosen based on the gain, signal bandwidth, low noise and (...)
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SOT-23 (DBV) 5 View options

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