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Product details

Parameters

Number of supplies monitored 1 Threshold voltage 1 (Typ) (V) 2.93, 4.55 Features Active-low enable, Manual reset, Watchdog timer Reset threshold accuracy (%) 2.4 Output driver type/reset output Active-low, Push-pull Time delay (ms) 25 Rating Catalog Watchdog timer WDI (sec) 0.2 Operating temperature range (C) -40 to 85 open-in-new Find other Supervisor & reset ICs

Package | Pins | Size

SOT-23 (DBV) 5 5 mm² 2.9 x 1.6 open-in-new Find other Supervisor & reset ICs

Features

  • Power-On reset generator with fixed delay time of 200 ms (TPS3823/4/5/8) or 25 ms (TPS3820)
  • Manual reset input (TPS3820/3/5/8)
  • Reset output available in active-low (TPS3820/3/4/5), active-high (TPS3824/5), and open drain (TPS3828)
  • Supply voltage supervision range:
    2.5 V, 3 V, 3.3 V, 5 V
  • Watchdog timer (TPS3820/3/4/8)
  • Supply current of 15 µA (Typical)
  • 5-Pin SOT-23 package
  • Temperature range: −40°C to 85°C (−40°C to 125°C for TPS3823A-33)

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Description

The TPS382x family of supervisors provide circuit initialization and timing supervision, primarily for DSP and processor-based systems. During power on, RESET asserts when the supply voltage VDD becomes greater than 1.1 V. Thereafter, the supply voltage supervisor monitors VDD and keeps RESET active low as long as VDD remains less than the threshold voltage, VIT−. An internal timer delays the return of the output to the inactive state (high) to ensure proper system reset. The delay time, td, starts after VDD has risen above the threshold voltage (VIT− + VHYS). When the supply voltage drops below the threshold voltage VIT−, the output becomes active (low) again. No external components are required. All the devices of this family have a fixed-sense threshold voltage, VIT–, set by an internal voltage divider. The TPS382x family also offers watchdog time out options of 200 ms (TPS3820) and 1.6 s (TPS3823/4/8).

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Exact equivalent in functionality and parametrics to the compared device:
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Technical documentation

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No results found. Please clear your search and try again. View all 7
Type Title Date
* Datasheet TPS382x Voltage Monitor With Watchdog Timer datasheet (Rev. M) Jul. 23, 2020
Application note Voltage Supervisors (Reset ICs): Frequently Asked Questions (FAQs) (Rev. A) Mar. 17, 2020
Selection guide Voltage Supervisors (Reset ICs) Quick Reference Guide (Rev. H) Feb. 28, 2020
E-book Voltage Supervisor and Reset ICs: Tips, Tricks and Basics Jun. 28, 2019
Application note Latching a Voltage Supervisor (Reset IC) (Rev. A) Apr. 05, 2019
Selection guide Power Management Guide 2018 (Rev. R) Jun. 25, 2018
Application note Disabling the Watchdog Timer for TI's Family of Supervisors Oct. 30, 2003

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
49
Description
The TPS382-Q1EVM evaluation module (EVM) has five different TPS382x-Q1 devices to let you evaluate and test the different features of the product family.  The EVM includes devices with 2.5-V, 3-V, 3.3-V and 5-V fixed monitoring, watchdog input, manual reset (...)
Features
  • Five different TPS382x-Q1 devices
  • Watchdog input
  • Manual reset jumpers
  • Push-pull and open-drain outputs

Design tools & simulation

SIMULATION TOOL Download
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Features
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)

Reference designs

REFERENCE DESIGNS Download
Spectrum Analyzer Signal Conditioning and Processing for Capturing Arc Signatures Reference Design
TIDA-00929 — The TIDA-00929 TI design demonstrates bandwidth optimized analog front end (AFE) and real-time FIR implementation using low power to capture broadband frequency spectrum in any waveform. Operational amplifier in each signal path is chosen based on the gain, signal bandwidth, low noise, close to the (...)
document-generic Schematic

CAD/CAE symbols

Package Pins Download
SOT-23 (DBV) 5 View options

Ordering & quality

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