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Product details

Parameters

DDR memory type DDR, DDR2, DDR3, DDR3L, DDR4, LPDDR2, LPDDR3 Control mode Current Mode, D-CAP Iout VDDQ (Max) (A) 25 Iout VTT (Max) (A) 3 Iq (Typ) (mA) 0.8 Output VDDQ, VREF, VTT Vin (Min) (V) 3 Vin (Max) (V) 28 Features Complete Solution, Shutdown Pin for S3 Rating Catalog Operating temperature range (C) -40 to 85 open-in-new Find other DDR memory power ICs

Package | Pins | Size

HTSSOP (PWP) 20 42 mm² 6.5 x 6.4 VQFN (RGE) 24 16 mm² 4 x 4 open-in-new Find other DDR memory power ICs

Features

  • Synchronous Buck Controller (VDDQ)
    • Wide-Input Voltage Range: 3.0-V to 28-V
    • D−CAP™ Mode with 100-ns Load Step Response
    • Current Mode Option Supports Ceramic Output Capacitors
    • Supports Soft-Off in S4/S5 States
    • Current Sensing from RDS(on) or Resistor
    • 2.5-V (DDR), 1.8-V (DDR2), Adjustable to
      1.5-V (DDR3), 1.35-V (DDR3L), 1.2-V (LPDDR3 and DDR4) or
      Output Range 0.75-V to 3.0-V
    • Equipped with Powergood, Overvoltage Protection and Undervoltage Protection
  • 3-A LDO (VTT), Buffered Reference (VREF)
    • Capable to Sink and Source 3 A
    • LDO Input Available to Optimize Power Losses
    • Requires only 20-µF Ceramic Output Capacitor
    • Buffered Low Noise 10-mA VREF Output
    • Accuracy ±20 mV for both VREF and VTT
    • Supports High-Z in S3 and Soft-Off in S4/S5
    • Thermal Shutdown

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Description

The TPS51116 provides a complete power supply for DDR/SSTL-2, DDR2/SSTL-18, DDR3/SSTL-15, DDR3L, LPDDR3 and DDR4 memory systems. It integrates a synchronous buck controller with a 3-A sink/source tracking linear regulator and buffered low noise reference. The device offers the lowest total solution cost in systems where space is at a premium. The synchronous controller runs fixed 400-kHz, pseudo-constant frequency PWM with an adaptive on-time control that can be configured in D-CAP™ Mode for ease of use and fastest transient response or in current mode to support ceramic output capacitors. The 3-A sink/source LDO maintains fast transient response only requiring 20-µF (2 × 10 µF) of ceramic output capacitance. In addition, the LDO supply input is available externally to significantly reduce the total power losses. The device supports all of the sleep state controls placing VTT at high-Z in S3 (suspend to RAM) and discharging VDDQ, VTT and VTTREF (soft-off) in S4/S5 (suspend to disk). The device has all of the protection features including thermal shutdown and is offered in both a 20-pin HTSSOP PowerPAD™ package and 24-pin 4 × 4 QFN.

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Technical documentation

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Type Title Date
* Datasheet TPS51116 Complete DDR, DDR2, DDR3, DDR3L, LPDDR3 and DDR4 Power Solution Synchronous Buck Controller, 3-A LDO, Buffered Reference datasheet (Rev. J) Nov. 16, 2017
Application note DDR VTT Power Solutions: A Competitive Analysis (Rev. A) Jul. 09, 2020
Selection guide Power Management Guide 2018 (Rev. R) Jun. 25, 2018
Selection guide Control-Mode Quick Reference Guide (Rev. A) Sep. 14, 2017
Technical article Design advantage of D-CAP control topology Apr. 13, 2017
Technical article D-CAP3 – A sequel better than the original May 07, 2015
Technical article Power Tips - DDR memory is everywhere! Mar. 01, 2014
More literature Computing DDR DC-DC Power Solutions Aug. 22, 2012
Application note Intel Core i3, i5, i7 [Arrandale] Reference Design Jul. 21, 2010
Application note Intel EP80579 Tolopai System-on-Chip Reference Design Jul. 21, 2010
Technical article Embedded Computers with TI Power in a myriad of applications May 15, 2010
Application note Pwr Ref Design f/'C6472 12-Vin Digital Pwr Controllers and LDOs Apr. 28, 2010
Application note Power Two Xilinx(TM) LX240 Virtex-6(TM) Devices Apr. 20, 2010
Application note Power Ref Design for TMS320C6472 5Vin DC/DC Converters (1x C6472) Mar. 31, 2010
Application note 'C6472 12Vin Flexible Pwr Design Using DCDC Controllers and LDOs (8x C6472) Mar. 26, 2010
Application note Power Reference Design for the 'C6472, 12V DCDC Controllers, and LDOs Mar. 26, 2010
Application note TMS320C6472 5V Input Pwr Design, Integrated FET DC/DC Converters and Controllers Mar. 26, 2010
User guide Using the TPS51116 (Rev. A) Nov. 12, 2008
Application note Cyclone™ III FPGA Starter Kit Power Reference Design Mar. 27, 2008
Application note DDR2 Power Solutions for Notebooks May 24, 2004

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
document-generic User guide
49
Description

The TPS51116EVM evaluation module (EVM) is a dual-output converter for DDR and DDRII memory modules. It uses a 10 A synchronous buck converter to provide the core voltage (VDDQ) for DDR memory modules. The EVM is designed to use a 4.5 V to 28 V supply voltage and a 4.75 V to (...)

Features
  • Up to 85% efficiency on the VDDQ switching regulator output
  • Dual switching regulator / LDO output for both DDR core and termination voltages
  • ± 3 A sink/source termination voltage LDO regulator
  • 10 mA termination reference voltage for DDR input reference
  • User selectable DDR and DDRII or externally referenced (...)

Design tools & simulation

SIMULATION MODEL Download
SLIM076B.ZIP (101 KB) - PSpice Model
SIMULATION MODEL Download
SLUM166.TSC (224 KB) - TINA-TI Reference Design
SIMULATION MODEL Download
SLUM167.ZIP (58 KB) - TINA-TI Spice Model

Reference designs

REFERENCE DESIGNS Download
Complete Power Solution for DDR or DDR2 Memory Applications
PMP1516 This DDR reference design provides a VDDQ of 2.5V @ 6A and a VTT of 1.25V. The 2.5V sync buck converter achieves an efficiency of 92% while the 1.25V minimizes area by implementing a built-in LDO and has excellent tracking performance.
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Altera Cyclone III FPGA Power Management Reference Design
PMP2543 The Cyclone III power management design is a complete, non-isolated power solution and provides all 5 required rails for powering the FPGA. The design also includes complete power solutions for DDR Memory VTT and VDDQ rails and USB power. This design is optimized to power the Altera 3C25F324 starter (...)
document-generic Schematic document-generic User guide
Design files
REFERENCE DESIGNS Download
REFERENCE DESIGNS Download
Single Chip DDR3 Supply using the TPS51116
PMP3130 — PMP3130 uses the TPS51116 to generate a DDR3 supply for VDDQ and VTT. The VDDQ supply is generated from single cell lithium ion battery to 1.5V at 4A using a synchronous buck converter. The VTT supply is generated using a LDO from 1.5V to 0.75V at up to 3A load current. The TPS51116 is designed to (...)

CAD/CAE symbols

Package Pins Download
HTSSOP (PWP) 20 View options
VQFN (RGE) 24 View options

Ordering & quality

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  • Ongoing reliability monitoring

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