TPS720

ACTIVE

350-mA, low-VIN (1.1-V), high-PSRR, low-IQ, low-dropout voltage regulator with enable

Product details

Output options Fixed Output Iout (max) (A) 0.35 Vin (max) (V) 4.5 Vin (min) (V) 1.1 Vout (max) (V) 1.8 Vout (min) (V) 0.9 Fixed output options (V) 0.9, 1, 1.1, 1.2, 1.3, 1.32, 1.5, 1.7, 1.8, 2.3 Noise (µVrms) 48 Iq (typ) (mA) 0.038 Thermal resistance θJA (°C/W) 67 Rating Catalog Load capacitance (min) (µF) 2.2 Regulated outputs (#) 1 Features Enable, Soft start Accuracy (%) 2 PSRR at 100 KHz (dB) 55 Dropout voltage (Vdo) (typ) (mV) 110 Operating temperature range (°C) -40 to 125
Output options Fixed Output Iout (max) (A) 0.35 Vin (max) (V) 4.5 Vin (min) (V) 1.1 Vout (max) (V) 1.8 Vout (min) (V) 0.9 Fixed output options (V) 0.9, 1, 1.1, 1.2, 1.3, 1.32, 1.5, 1.7, 1.8, 2.3 Noise (µVrms) 48 Iq (typ) (mA) 0.038 Thermal resistance θJA (°C/W) 67 Rating Catalog Load capacitance (min) (µF) 2.2 Regulated outputs (#) 1 Features Enable, Soft start Accuracy (%) 2 PSRR at 100 KHz (dB) 55 Dropout voltage (Vdo) (typ) (mV) 110 Operating temperature range (°C) -40 to 125
DSBGA (YZU) 5 2.02 mm² 1.25 x 1.616 WSON (DRV) 6 4 mm² 2 x 2
  • 350-mA High-Performance LDO
  • Low Quiescent Current: 38 µA
  • Excellent Load Transient Response:
    ±15 mV for ILOAD = 0 mA to 350 mA in 1 µs
  • Excellent Line Transient Response:
    ΔVOUT = ±2 mV for ΔVBIAS = ±600 mV in 1 µs
    ΔVOUT = ±200 µV for ΔVIN = ±400 mV in 1 µs
  • Low Noise: 48 µVRMS (10 Hz to 100 kHz)
  • 80 dB VIN PSRR (10 Hz to 10 kHz)
  • 70 dB VBIAS PSRR (10 Hz to 10 kHz)
  • Fast Start-Up Time: 140 µs
  • Built-In Soft-Start With Monotonic VOUT Rise and Start-Up Current Limited to 100 mA + ILOAD
  • Overcurrent and Thermal Protection
  • Low Dropout: 110 mV at ILOAD = 350 mA
  • Stable with 2.2-µF Output Capacitor
  • Available in 1.33 mm × 0.96 mm DSBGA-5 and 2 mm × 2 mm SON-6 Packages
  • 350-mA High-Performance LDO
  • Low Quiescent Current: 38 µA
  • Excellent Load Transient Response:
    ±15 mV for ILOAD = 0 mA to 350 mA in 1 µs
  • Excellent Line Transient Response:
    ΔVOUT = ±2 mV for ΔVBIAS = ±600 mV in 1 µs
    ΔVOUT = ±200 µV for ΔVIN = ±400 mV in 1 µs
  • Low Noise: 48 µVRMS (10 Hz to 100 kHz)
  • 80 dB VIN PSRR (10 Hz to 10 kHz)
  • 70 dB VBIAS PSRR (10 Hz to 10 kHz)
  • Fast Start-Up Time: 140 µs
  • Built-In Soft-Start With Monotonic VOUT Rise and Start-Up Current Limited to 100 mA + ILOAD
  • Overcurrent and Thermal Protection
  • Low Dropout: 110 mV at ILOAD = 350 mA
  • Stable with 2.2-µF Output Capacitor
  • Available in 1.33 mm × 0.96 mm DSBGA-5 and 2 mm × 2 mm SON-6 Packages

The TPS720 family of dual rail, low-dropout linear regulators (LDOs) offers outstanding ac performance (PSRR, load and line transient response), while consuming a very low quiescent current of 38 µA.

The VBIAS rail that powers the control circuit of the LDO draws very low current (on the order of the quiescent current of the LDO) and can be connected to any power supply that is equal to or greater than 1.4 V above the output voltage. The main power path is through VIN, which can be a lower voltage than VBIAS; it can be as low as VOUT + VDO, increasing the efficiency of the solution in many power-sensitive applications. For example, VIN can be an output of a high-efficiency, DC-DC step-down regulator.

The TPS720 supports a novel feature in which the output of the LDO regulates under light loads when the IN pin is left floating. The light-load drive current is sourced from VBIAS under this condition. This feature is particularly useful in power-saving applications where the DC-DC converter connected to the IN pin is disabled but the LDO is still required to regulate the voltage to a light load.

The TPS720 is stable with ceramic capacitors and uses an advanced BICMOS fabrication process that yields a dropout of 110 mV at a 350-mA output load. The TPS720 has the unique feature of providing a monotonic VOUT rise (overshoot limited to 3%) with VIN inrush current limited to 100 mA + ILOAD with an output capacitor of 2.2 µF.

The TPS720 uses a precision voltage reference and feedback loop to achieve overall accuracy of 2% over load, line, process, and temperature extremes. An ultra-small DSBGA package makes the TPS720 ideal for handheld applications. The TPS720 is also available in a SON-8 package. This family of devices is fully specified over the temperature range of
TJ = –40°C to 125°C.

The TPS720 family of dual rail, low-dropout linear regulators (LDOs) offers outstanding ac performance (PSRR, load and line transient response), while consuming a very low quiescent current of 38 µA.

The VBIAS rail that powers the control circuit of the LDO draws very low current (on the order of the quiescent current of the LDO) and can be connected to any power supply that is equal to or greater than 1.4 V above the output voltage. The main power path is through VIN, which can be a lower voltage than VBIAS; it can be as low as VOUT + VDO, increasing the efficiency of the solution in many power-sensitive applications. For example, VIN can be an output of a high-efficiency, DC-DC step-down regulator.

The TPS720 supports a novel feature in which the output of the LDO regulates under light loads when the IN pin is left floating. The light-load drive current is sourced from VBIAS under this condition. This feature is particularly useful in power-saving applications where the DC-DC converter connected to the IN pin is disabled but the LDO is still required to regulate the voltage to a light load.

The TPS720 is stable with ceramic capacitors and uses an advanced BICMOS fabrication process that yields a dropout of 110 mV at a 350-mA output load. The TPS720 has the unique feature of providing a monotonic VOUT rise (overshoot limited to 3%) with VIN inrush current limited to 100 mA + ILOAD with an output capacitor of 2.2 µF.

The TPS720 uses a precision voltage reference and feedback loop to achieve overall accuracy of 2% over load, line, process, and temperature extremes. An ultra-small DSBGA package makes the TPS720 ideal for handheld applications. The TPS720 is also available in a SON-8 package. This family of devices is fully specified over the temperature range of
TJ = –40°C to 125°C.

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Technical documentation

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Type Title Date
* Data sheet TPS720 350 mA, Ultra-Low VIN, RF Low-Dropout Linear Regulator With Bias Pin datasheet (Rev. E) PDF | HTML 30 Sep 2015
Application note LDO Noise Demystified (Rev. B) PDF | HTML 18 Aug 2020
Application note A Topical Index of TI LDO Application Notes (Rev. F) 27 Jun 2019
Selection guide Low Dropout Regulators Quick Reference Guide (Rev. P) 21 Mar 2018
Application note LDO PSRR Measurement Simplified (Rev. A) PDF | HTML 09 Aug 2017
EVM User's guide TPS720xxDRVEVM Evaluation Module 29 Apr 2010
Application note Power Reference Design for the 'C6472, 12V DCDC Controllers, and LDOs 26 Mar 2010
Analog Design Journal Q2 2009 Issue Analog Applications Journal 01 May 2009
Analog Design Journal Taming linear-regulator inrush currents 01 May 2009
User guide TPS720xx 19 Aug 2008
Application note Inrush Current Limit in the TPS720xx 06 Jun 2008

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

TPS720105DRVEVM — TPS720105 LDO Linear Regulator in DRV Package Evaluation Module

The TPS720105DRVEVM is a fully assembled and tested circuit for evaluating the TPS720105 low-dropout linear regulator in the DRV (2mm x 2mm SON-6) package.
User guide: PDF
Not available on TI.com
Simulation model

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SBVM248.ZIP (21 KB) - PSpice Model
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TPS72010 PSpice Transient Model

SBVM557.ZIP (102 KB) - PSpice Model
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TPS72010 Unencrypted PSpice Transient Model

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TPS720102 PSpice Transient Model

SLVMCN6.ZIP (108 KB) - PSpice Model
Simulation model

TPS720102 Unencrypted PSpice Transient Model

SLVMCN9.ZIP (2 KB) - PSpice Model
Simulation model

TPS720105 PSpice Transient Model

SLVMBL2.ZIP (99 KB) - PSpice Model
Simulation model

TPS720105 Unencrypted PSpice Transient Model

SLVMBL1.ZIP (2 KB) - PSpice Model
Simulation model

TPS72011 PSpice Transient Model (Rev. A)

SBVM277A.ZIP (22 KB) - PSpice Model
Simulation model

TPS720115 Unencrypted PSpice Transient Model (Rev. A)

SBVM254A.ZIP (22 KB) - PSpice Model
Simulation model

TPS72013 Unencrypted PSpice Transient Model (Rev. A)

SBVM249A.ZIP (22 KB) - PSpice Model
Simulation model

TPS720132 PSpice Transient Model

SLVMCN5.ZIP (109 KB) - PSpice Model
Simulation model

TPS720132 Unencrypted PSpice Transient Model

SLVMCN8.ZIP (2 KB) - PSpice Model
Simulation model

TPS72015 PSpice Transient Model

SBVM247.ZIP (24 KB) - PSpice Model
Simulation model

TPS72018 PSpice Transient Model

SBVM567.ZIP (105 KB) - PSpice Model
Simulation model

TPS72018 Unencrypted PSpice Transient Model

SBVM568.ZIP (2 KB) - PSpice Model
Simulation model

TPS72023 PSpice Transient Model

SLVMCO0.ZIP (135 KB) - PSpice Model
Simulation model

TPS72023 Unencrypted PSpice Transient Model

SLVMCN7.ZIP (2 KB) - PSpice Model
Simulation model

TPS72025 PSpice Transient Model

SBVM562.ZIP (110 KB) - PSpice Model
Simulation model

TPS72025 Unencrypted PSpice Transient Model

SBVM561.ZIP (2 KB) - PSpice Model
Simulation model

TPS72027 PSpice Transient Model

SLVMBL4.ZIP (104 KB) - PSpice Model
Simulation model

TPS72027 Unencrypted PSpice Transient Model

SLVMBL3.ZIP (2 KB) - PSpice Model
Simulation model

TPS72028 PSpice Transient Model

SBVM564.ZIP (106 KB) - PSpice Model
Simulation model

TPS72028 Unencrypted PSpice Transient Model

SBVM563.ZIP (2 KB) - PSpice Model
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TPS720285 PSpice Transient Model

SBVM566.ZIP (106 KB) - PSpice Model
Simulation model

TPS720285 Unencrypted PSpice Transient Model

SBVM565.ZIP (2 KB) - PSpice Model
Simulation model

TPS72029 PSpice Transient Model

SBVM560.ZIP (106 KB) - PSpice Model
Simulation model

TPS72029 Unencrypted PSpice Transient Model

SBVM559.ZIP (2 KB) - PSpice Model
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TPS72030 PSpice Transient Model

SBVM570.ZIP (106 KB) - PSpice Model
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TPS72030 Unencrypted PSpice Transient Model

SBVM569.ZIP (2 KB) - PSpice Model
Simulation model

TPS72033 PSpice Transient Model

SLVMBL0.ZIP (109 KB) - PSpice Model
Simulation model

TPS72033 Unencrypted PSpice Transient Model

SLVMBL5.ZIP (2 KB) - PSpice Model
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Package Pins Download
DSBGA (YZU) 5 View options
WSON (DRV) 6 View options

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