Product details


Type PHY Protocols PCIe Applications PCIe Number of channels (#) 1 Speed (Max) (Gbps) 2.5 Supply voltage (V) 1.5, 1.8, 3.3 Rating Catalog Operating temperature range (C) 0 to 70 open-in-new Find other PCIe, SAS & SATA ICs

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NFBGA (ZWS) 100 open-in-new Find other PCIe, SAS & SATA ICs


  • X1 PCI Express™ Serial Link
    • PCI Express 1.1 Compliant
    • Selectable Reference Clock (100 MHz, 125 MHz)
    • Low-Power Capability
  • TI-PIPE MAC Interface
    • Source-Synchronous TX and RX Ports
    • 125 MHz TX/RX Clocks
    • Selectable 16-Bit SDR or 8-Bit DDR Mode
  • 100-Pin MicroStar™ BGA Package
  • Selectable 1.5-V or 1.8-V LVCMOS Buffers.

TI and MicroStar BGA are trademarks of Texas Instruments Incorporated
PCI Express is a trademark of PCI-SIG

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The XIO1100 is a PCI Express. PHY that is compliant with PCI Express Base Specification Revision 1.1 and that interfaces the PCI Express Media Access Layer (MAC) to a PCI Express serial link by using a modified version of the interface described in PHY Interface for the PCI Express. Architecture (also known as PIPE interface) by Intel Corporation. This modified version of the PIPE interface is referred to as a TI-PIPE interface throughout this data manual.

The TI-PIPE interface is a pin-configurable interface that can be configured as either a 16-bit or an 8-bit interface.

  • The 16-bit TI-PIPE interface is a 125 MHz 16-bit parallel interface with a 16-bit output bus (RXDATA) that is clocked by the RXCLK output clock and a 16-bit input bus (TXDATA) that is clocked by the TXCLK input clock. Both buses are clocked using Single Data Rate (SDR) clocking in which the data transitions are on the rising edge of the associated clock.
  • The 8-bit TI-PIPE interface is a 250 MHz 8-bit parallel interface with an 8-bit output bus (RXDATA) that is clocked by the RXCLK output clock and an 8-bit input bus (TXDATA) that is clocked by the TXCLK input clock. Both buses are clocked using Double Data Rate (DDR) clocking in which the data transitions are on both the rising edge and the falling edge of the clock.

The XIO1100 PHY interfaces to a 2.5 Gbps PCI Express serial link with a transmit differential pair (TXP and TXN) and a receive differential pair (RXP and RXN). Incoming data at the XIO1100 PHY receive differential pair (RXP and RXN) is forwarded to the MAC on the RXDATA output bus. Data received from the MAC on the TXDATA input bus is forwarded to the XIO1100 PHY transfer differential pair (TXP and TXN).

The XIO1100 is also responsible for handling the 8B/10B encoding/decoding and scrambling/unscrambling of the outgoing data. In addition, XIO1100 can recover/interpolate the clock on the receiver side based on the transitions guaranteed by the use of the 8B/10B mechanism and supply this to the receive side of the data link layer logic.

In addition to the TI-PIPE interface, the XIO1100 has some TI-proprietary side-band signals that some customers may wish to use to take advantage of additional XIO1100 low-power state features (for example, disabling the PLL during the L1 power state).

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Technical documentation

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Type Title Date
* Data sheet XIO1100 Data Manual datasheet (Rev. C) Aug. 18, 2011
* Errata XIO1100 Data Manual Errata Jul. 12, 2006
* User guide HSSC MicroStar BGA Discontinued and Redesigned Jan. 18, 2021
More literature PCI Express PHY XIO1100 Quick Reference Card (Rev. A) May 16, 2008
Application note XIO1100: NAND TREE TEST Aug. 24, 2007

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