Gehäuseinformationen
| Gehäuse | Pins TLGA (NPP) | 80 |
| Betriebstemperaturbereich (°C) -40 to 85 |
| Gehäusemenge | Träger 3.000 | LARGE T&R |
Merkmale von CDCDB2000
- 20 LP-HCSL outputs with integrated 85Ω output terminations
- 8 hardware output enable (OE#) controls
- Additive phase jitter after DB2000QL filter: < 0.08ps rms
- Supports PCIe Gen 6 and Gen 7 Common Clock (CC) and Individual Reference (IR) architectures
- Spread spectrum-compatible
- Cycle-to-cycle jitter: < 50ps
- Output-to-output skew: < 50ps
- Input-to-output delay: < 3ns
- 3.3V core and IO supply voltages
- Hardware-controlled low power mode (PD#)
- Side-Band Interface (SBI) for output control in PD# mode
- 9 selectable SMBus addresses
- Power consumption: < 600mW
- 6mm × 6mm, 80-pin TLGA/GQFN package
Beschreibung von CDCDB2000
The CDCDB2000 is a 20-output LP-HCSL, DB2000QL compliant, clock buffer capable of distributing the reference clock for PCIe Gen 1-7, QuickPath Interconnect (QPI), UPI, SAS, and SATA interfaces. The SMBus, SBI, and 8 output enable pins allow the configuration and control of all 20 outputs individually. The CDCDB2000 is a DB2000QL derivative buffer and meets or exceeds the system parameters in the DB2000QL specification. The CDCDB2000 is packaged in a 6mm × 6mm TLGA/GQFN package with 80 leads.