CDCLVP215

Name: CDCLVP215
Brand: TI
SKU: CDCLVP215
Price: 5.128 USD

AKTIV

Zwei 1:5-Hochgeschwindigkeits-LVPECL-Fan-Out-Puffer

Jetzt bestellen

Datenblatt

document-pdfAcrobat Low-Voltage Dual Differential 1:5 LVPECL Clock Driver datasheet (Rev. B) (Englisch)

CDCLVP215

AKTIV

Datenblatt

Jetzt bestellen

Produktdetails

Number of outputs

10

Additive RMS jitter (typ) (fs)

300

Core supply voltage (V)

2.5, 3.3

Output supply voltage (V)

2.5, 3.3

Output skew (ps)

30

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Output type

LVPECL

Input type

LVPECL

Number of outputs

10

Additive RMS jitter (typ) (fs)

300

Core supply voltage (V)

2.5, 3.3

Output supply voltage (V)

2.5, 3.3

Output skew (ps)

30

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Output type

LVPECL

Input type

LVPECL

VQFN (RHB)

32

25 mm² 5 x 5

2× One Differential Clock Input Pair LVPECL to 5 Differential LVPECL Clock Outputs
Fully Compatible With LVPECL/LVECL
Supports a Wide Supply Voltage Range From 2.375 V to 3.8 V
Open Input Default State
Low-Output Skew (Typ 15 ps) for Clock-Distribution Applications
V_BB Reference Voltage Output for Single-Ended Clocking
Available in the QFN32 Package
Frequency Range From DC to 3.5 GHz
Pin-to-Pin Compatible With the MC100 Series EP111, LVEP210, ES6111, LVEP111
APPLICATIONS
- Designed for Driving 50- Transmission Lines High Performance Clock Distribution

2× One Differential Clock Input Pair LVPECL to 5 Differential LVPECL Clock Outputs
Fully Compatible With LVPECL/LVECL
Supports a Wide Supply Voltage Range From 2.375 V to 3.8 V
Open Input Default State
Low-Output Skew (Typ 15 ps) for Clock-Distribution Applications
V_BB Reference Voltage Output for Single-Ended Clocking
Available in the QFN32 Package
Frequency Range From DC to 3.5 GHz
Pin-to-Pin Compatible With the MC100 Series EP111, LVEP210, ES6111, LVEP111
APPLICATIONS
- Designed for Driving 50- Transmission Lines High Performance Clock Distribution

The CDCLVP215 clock driver distributes two times one differential clock pair of LVPECL, (CLKA, CLKB) to 5 pairs of differential LVPECL clock (QA0..QA4, QB0..QB4) outputs with minimum skew for clock distribution. The CDCLVP215 specifies low output-to-output skew. The CDCLVP215 is specifically designed for driving 50- transmission lines. When an output pair is not used, leaving it open is recommended to reduce power consumption. If only one of the output pairs is used, the other output pair must be identically terminated to 50 .

The V_BB reference voltage output is used if single-ended input operation is required. In this case, the V_BB pin should be connected to CLKA or CLKB and bypassed to GND via a 10-nF capacitor.

However, for high-speed performance up to 3.5 GHz, the differential mode is strongly recommended.

The CDCLVP215 is characterized for operation from –40°C to 85°C.

The CDCLVP215 clock driver distributes two times one differential clock pair of LVPECL, (CLKA, CLKB) to 5 pairs of differential LVPECL clock (QA0..QA4, QB0..QB4) outputs with minimum skew for clock distribution. The CDCLVP215 specifies low output-to-output skew. The CDCLVP215 is specifically designed for driving 50- transmission lines. When an output pair is not used, leaving it open is recommended to reduce power consumption. If only one of the output pairs is used, the other output pair must be identically terminated to 50 .

The V_BB reference voltage output is used if single-ended input operation is required. In this case, the V_BB pin should be connected to CLKA or CLKB and bypassed to GND via a 10-nF capacitor.

However, for high-speed performance up to 3.5 GHz, the differential mode is strongly recommended.

The CDCLVP215 is characterized for operation from –40°C to 85°C.

filter

Andere Taktpuffer suchen

Herunterladen Video mit Transkript ansehen Video

Alle anzeigen 1

Top-Dokumentation	Typ	Titel	Format-Optionen	Datum
*	Data sheet	Low-Voltage Dual Differential 1:5 LVPECL Clock Driver datasheet (Rev. B)		02 Nov 2009

Design und Entwicklung

Weitere Bedingungen oder erforderliche Ressourcen enthält gegebenenfalls die Detailseite, die Sie durch Klicken auf einen der unten stehenden Titel erreichen.

Designtool

CLOCK-TREE-ARCHITECT — Programmiersoftware Clock Tree Architect

Der Taktbaum-Architekt ist ein Taktbaum-Synthesetool, das Ihren Designprozess optimiert, indem es Taktbaumlösungen auf der Grundlage Ihrer Systemanforderungen erzeugt. Das Tool zieht Daten aus einer umfangreichen Datenbank von Taktgeberprodukten, um eine Multi-Chip-Taktlösung auf Systemebene zu (...)

Jetzt entwickeln

Designtool

PLLATINUMSIM-SW — PLL loop filter, phase noise, lock time, and spur simulation tool

PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.

Unterstützte Produkte und Hardware

Download-Optionen

Simulationstool

PSPICE-FOR-TI — PSpice® für TI Design-und Simulationstool

PSpice® für TI ist eine Design- und Simulationsumgebung, welche Sie dabei unterstützt, die Funktionalität analoger Schaltungen zu evaluieren. Diese Design- und Simulationssuite mit vollem Funktionsumfang verwendet eine analoge Analyse-Engine von Cadence®. PSpice für TI ist kostenlos erhältlich und (...)

Anfordern

Gehäuse	Pins	CAD-Symbole, Footprints und 3D-Modelle
VQFN (RHB)	32	Ultra Librarian

Es gelten die allgemeinen Geschäftsbedingungen von TI für Evaluierungsartikel.

CDCLVP215

Zwei 1:5-Hochgeschwindigkeits-LVPECL-Fan-Out-Puffer

CDCLVP215

Produktdetails

Ähnliche Produkte, die für Sie interessant sein könnten

Ähnliche Funktionalität wie verglichener Baustein

Technische Dokumentation

Design und Entwicklung

CLOCK-TREE-ARCHITECT — Programmiersoftware Clock Tree Architect

PLLATINUMSIM-SW — PLL loop filter, phase noise, lock time, and spur simulation tool

Unterstützte Produkte und Hardware

PSPICE-FOR-TI — PSpice® für TI Design-und Simulationstool

Bestellen & Qualität

Support und Schulungen

TI E2E™-Foren mit technischem Support von TI-Ingenieuren

Videoreihe

Videos

Download-Möglichkeiten

PLLATINUMSIM-SW — PLL loop filter, phase noise, lock time, and spur simulation tool

Taktpuffer

Taktgeneratoren

Takt-Jitter-Cleaner

Oszillatoren

HF-PLLs und Synthesizer

Hardware-Entwicklung

Dokumentation

Versionsinformationen

Neuheiten