Gehäuseinformationen
| Gehäuse | Pins TSSOP (PW) | 8 |
| Betriebstemperaturbereich (°C) -40 to 105 |
| Gehäusemenge | Träger 2.000 | LARGE T&R |
Merkmale von CDCS503-Q1
- Qualified for Automotive Applications
- AEC-Q100 Test Guidance With the Following Results:
- Device Temperature Grade 2
- –40°C to 105°C
Ambient Operating Temperature Range - Device HBM ESD Classification Level H2
- Device CDM ESD Classification Level C3B
- Part of a Family of Easy to Use Clock Generator
Devices With Optional Spread Spectrum Clocking (SSC) - Clock Multiplier With Selectable Output Frequency and Selectable SSC
- SSC Controllable Through Two External Pins
- ±0%, ±0.5%, ±1%, ±2% Center Spread
- Frequency Multiplication Selectable Between x1 or x4 With One External Control Pin
- Output Disable Through Control Pin
- Single 3.3 V Device Power Supply
- Wide Temperature Range –40°C to 105°C
- Low Space Consumption 8-Pin TSSOP Package
Beschreibung von CDCS503-Q1
The CDCS503-Q1 device is a spread spectrum capable, LVCMOS input clock buffer with selectable frequency multiplication.
It shares major functionality with the CDCS502 but uses a LVCMOS input stage instead of the crystal input stage of the CDCS502, and the CDCS503-Q1 has an output enable pin.
The device accepts a 3.3-V LVCMOS signal at the input.
The input signal is processed by a phased-locked loop (PLL), whose output frequency is either equal to the input frequency or multiplied by the factor of four.
The PLL is also able to spread the clock signal by ±0%, ±0.5%, ±1% or ±2% centered around the output clock frequency with a triangular modulation.
By this, the device can generate output frequencies between 8 MHz and 108 MHz with or without SSC.
A separate control pin can be used to enable or disable the output. The CDCS503-Q1 device operates in a 3.3-V environment.
It is characterized for operation from –40°C to 105°C, and available in an 8-pin TSSOP package.