Produktdetails

CPU 2 Arm Cortex-A15 Frequency (MHz) 1000 Coprocessors 4 Arm Cortex-M4 Graphics acceleration 1 2D, 2 3D Display type 1 HDMI, 3 LCD Protocols Ethernet PCIe 2 PCIe Gen 2 Hardware accelerators Audio Tracking, Image video accelerator, Viterbi decoder Features Multimedia Operating system Android, Linux, RTOS Security Cryptographic acceleration, Device attestation & anti-counterfeit, Hardware-enforced isolation, Secure boot, Secure debug, Secure storage, Software IP protection Rating Automotive Operating temperature range (°C) -40 to 125 Edge AI enabled No
CPU 2 Arm Cortex-A15 Frequency (MHz) 1000 Coprocessors 4 Arm Cortex-M4 Graphics acceleration 1 2D, 2 3D Display type 1 HDMI, 3 LCD Protocols Ethernet PCIe 2 PCIe Gen 2 Hardware accelerators Audio Tracking, Image video accelerator, Viterbi decoder Features Multimedia Operating system Android, Linux, RTOS Security Cryptographic acceleration, Device attestation & anti-counterfeit, Hardware-enforced isolation, Secure boot, Secure debug, Secure storage, Software IP protection Rating Automotive Operating temperature range (°C) -40 to 125 Edge AI enabled No
FCBGA (ABC) 760 529 mm² (23 mm × 23 mm)
  • Architecture designed for infotainment applications
  • Video, image, and graphics processing support
    • Full-HD video (1920 × 1080p, 60 fps)
    • Multiple video input and video output
    • 2D and 3D graphics
  • Dual Arm® Cortex®-A15 microprocessor subsystem
  • Up to two C66x floating-point VLIW DSP
    • Fully object-code compatible with C67x and C64x+
    • Up to thirty-two 16 x 16-Bit fixed-point multiplies per cycle
  • Up to 2.5MB of on-chip L3 RAM
  • Level 3 (L3) and level 4 (L4) interconnects
  • Two DDR2/DDR3/DDR3L memory interface (EMIF) modules
    • Supports up to DDR2-800 and DDR3-1066
    • Up to 2GB supported per EMIF
  • Dual Arm® Cortex®-M4 Image Processing Units (IPU)
  • Up to two Embedded Vision Engines (EVEs)
  • IVA subsystem
  • Display subsystem
    • Display controller with DMA engine and up to three pipelines
    • HDMI™ encoder: HDMI 1.4a and DVI 1.0 compliant
  • Video Processing Engine (VPE)
  • 2D-graphics accelerator (BB2D) subsystem
    • Vivante® GC320 core
  • Dual-core PowerVR® SGX544 3D GPU
  • Three Video Input Port (VIP) modules
    • Support for up to 10 multiplexed input ports
  • General-Purpose Memory Controller (GPMC)
  • Enhanced Direct Memory Access (EDMA) controller
  • 2-port gigabit ethernet (GMAC)
  • Sixteen 32-Bit general-purpose timers
  • 32-Bit MPU watchdog timer
  • Five Inter-Integrated Circuit (I2C™) ports
  • HDQ™/1-Wire® interface
  • SATA interface
  • MediaLB® (MLB) subsystem
  • Ten configurable UART/IrDA/CIR modules
  • Four Multichannel Serial Peripheral Interfaces (McSPI)
  • Quad SPI (QSPI)
  • Eight Multichannel Audio Serial Port (McASP) modules
  • SuperSpeed USB 3.0 dual-role device
  • Three high-speed USB 2.0 dual-role devices
  • Four Multimedia Card/Secure Digital/Secure Digital Input Output interfaces (MMC™/SD®/SDIO)
  • PCI-Express® 3.0 subsystems with two 5-Gbps lanes
    • One 2-lane gen2-compliant port
    • or Two 1-lane gen2-compliant ports
  • Dual Controller Area Network (DCAN) modules
    • CAN 2.0B protocol
  • Up to 247 General-Purpose I/O (GPIO) pins
  • Real-Time Clock SubSystem (RTCSS)
  • Device security features
    • Hardware crypto accelerators and DMA
    • Firewalls
    • JTAG® lock
    • Secure keys
    • Secure ROM and boot
  • Power, Reset, and Clock Management (PRCM)
  • On-chip debug with CTools technology
  • 28-nm CMOS technology
  • 23 mm × 23 mm, 0.8-mm pitch, 760-pin BGA (ABC)
  • Architecture designed for infotainment applications
  • Video, image, and graphics processing support
    • Full-HD video (1920 × 1080p, 60 fps)
    • Multiple video input and video output
    • 2D and 3D graphics
  • Dual Arm® Cortex®-A15 microprocessor subsystem
  • Up to two C66x floating-point VLIW DSP
    • Fully object-code compatible with C67x and C64x+
    • Up to thirty-two 16 x 16-Bit fixed-point multiplies per cycle
  • Up to 2.5MB of on-chip L3 RAM
  • Level 3 (L3) and level 4 (L4) interconnects
  • Two DDR2/DDR3/DDR3L memory interface (EMIF) modules
    • Supports up to DDR2-800 and DDR3-1066
    • Up to 2GB supported per EMIF
  • Dual Arm® Cortex®-M4 Image Processing Units (IPU)
  • Up to two Embedded Vision Engines (EVEs)
  • IVA subsystem
  • Display subsystem
    • Display controller with DMA engine and up to three pipelines
    • HDMI™ encoder: HDMI 1.4a and DVI 1.0 compliant
  • Video Processing Engine (VPE)
  • 2D-graphics accelerator (BB2D) subsystem
    • Vivante® GC320 core
  • Dual-core PowerVR® SGX544 3D GPU
  • Three Video Input Port (VIP) modules
    • Support for up to 10 multiplexed input ports
  • General-Purpose Memory Controller (GPMC)
  • Enhanced Direct Memory Access (EDMA) controller
  • 2-port gigabit ethernet (GMAC)
  • Sixteen 32-Bit general-purpose timers
  • 32-Bit MPU watchdog timer
  • Five Inter-Integrated Circuit (I2C™) ports
  • HDQ™/1-Wire® interface
  • SATA interface
  • MediaLB® (MLB) subsystem
  • Ten configurable UART/IrDA/CIR modules
  • Four Multichannel Serial Peripheral Interfaces (McSPI)
  • Quad SPI (QSPI)
  • Eight Multichannel Audio Serial Port (McASP) modules
  • SuperSpeed USB 3.0 dual-role device
  • Three high-speed USB 2.0 dual-role devices
  • Four Multimedia Card/Secure Digital/Secure Digital Input Output interfaces (MMC™/SD®/SDIO)
  • PCI-Express® 3.0 subsystems with two 5-Gbps lanes
    • One 2-lane gen2-compliant port
    • or Two 1-lane gen2-compliant ports
  • Dual Controller Area Network (DCAN) modules
    • CAN 2.0B protocol
  • Up to 247 General-Purpose I/O (GPIO) pins
  • Real-Time Clock SubSystem (RTCSS)
  • Device security features
    • Hardware crypto accelerators and DMA
    • Firewalls
    • JTAG® lock
    • Secure keys
    • Secure ROM and boot
  • Power, Reset, and Clock Management (PRCM)
  • On-chip debug with CTools technology
  • 28-nm CMOS technology
  • 23 mm × 23 mm, 0.8-mm pitch, 760-pin BGA (ABC)

DRA75x and DRA74x (Jacinto 6) infotainment applications processors are built to meet the intense processing needs of the modern infotainment-enabled automobile experiences.

The device enables Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers (ODMs) to quickly implement innovative connectivity technologies, speech recognition, audio streaming, and more. Jacinto 6 devices bring high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The devices also combine programmable video processing with a highly integrated peripheral set.

Programmability is provided by dual-core Arm® Cortex®-A15 RISC CPUs with Arm® Neon™ extension, TI C66x VLIW floating-point DSP core, and Vision AccelerationPac (with one or more EVEs). The Arm allows developers to keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.

Additionally, TI provides a complete set of development tools for the Arm, DSP, and EVE coprocessor, including C compilers and a debugging interface for visibility into source code.

The DRA75x and DRA74x Jacinto 6 processor family is qualified according to the AEC-Q100 standard.

DRA75x and DRA74x (Jacinto 6) infotainment applications processors are built to meet the intense processing needs of the modern infotainment-enabled automobile experiences.

The device enables Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers (ODMs) to quickly implement innovative connectivity technologies, speech recognition, audio streaming, and more. Jacinto 6 devices bring high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The devices also combine programmable video processing with a highly integrated peripheral set.

Programmability is provided by dual-core Arm® Cortex®-A15 RISC CPUs with Arm® Neon™ extension, TI C66x VLIW floating-point DSP core, and Vision AccelerationPac (with one or more EVEs). The Arm allows developers to keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.

Additionally, TI provides a complete set of development tools for the Arm, DSP, and EVE coprocessor, including C compilers and a debugging interface for visibility into source code.

The DRA75x and DRA74x Jacinto 6 processor family is qualified according to the AEC-Q100 standard.

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Technische Dokumentation

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Top-Dokumentation Typ Titel Format-Optionen Neueste englische Version herunterladen Datum
* Datenblatt DRA75x, DRA74x Infotainment Applications Processor Silicon Revision 2.0 datasheet (Rev. F) PDF | HTML 07.05.2019
* Benutzerhandbuch DRA75x, DRA74x Technical Reference Manual (SR2.0 & SR1.1) (Rev. H) PDF | HTML 24.05.2024
* Errata DRA75x, DRA74x Silicon Errata Automotive Infotainment Silicon Revision 2.0, 1.1 (Rev. K) PDF | HTML 08.09.2024
Anwendungshinweis Integrating virtual DRM between VISION SDK and PSDK on Jacinto6 SOC PDF | HTML 05.05.2021
Anwendungshinweis IVA-HD Sharing Between VISION-SDK and PSDKLA on Jacinto6 SoC PDF | HTML 24.08.2020
Anwendungshinweis AM57x, DRA7x, and TDA2x EMIF Tools (Rev. E) 06.01.2020
Anwendungshinweis Integrating New Cameras With Video Input Port on DRA7xx SoCs PDF | HTML 11.06.2019
Anwendungshinweis Achieving Early CAN Response on DRA7xx Devices 28.11.2018
Anwendungshinweis DRA74x_75x/DRA72x Performance (Rev. A) 31.10.2018
Anwendungshinweis Audio Post Processing Engine on Jacinto™ DRA7x Family of Devices 14.09.2018
Anwendungshinweis The Implementation of YUV422 Output for SRV 02.08.2018
Anwendungshinweis MMC DLL Tuning (Rev. B) 31.07.2018
Anwendungshinweis Integrating AUTOSAR on TI SoC: Fundamentals 18.06.2018
Anwendungshinweis ECC/EDC on TDAxx (Rev. B) 13.06.2018
Anwendungshinweis Tools and Techniques to Root Case Failures in Video Capture Subsystem 12.06.2018
Anwendungshinweis Sharing VPE Between VISIONSDK and PSDKLA 04.05.2018
Anwendungshinweis Android Boot Optimization on DRA7xx Devices (Rev. A) 13.02.2018
Anwendungshinweis Flashing Utility - mflash 09.01.2018
Anwendungshinweis Using Peripheral Boot and DFU for Rapid Development on Jacinto 6 Devices (Rev. A) 30.11.2017
Anwendungshinweis Jacinto6 Spread Spectrum Clocking Configuration (Rev. A) 27.11.2017
Anwendungshinweis Optimizing DRA7xx and TDA2xx Processors for use with Video Display SERDES (Rev. B) 07.11.2017
Anwendungshinweis A Guide to Debugging With CCS on the DRA75x, DRA74x, TDA2x and TDA3x Family of D (Rev. B) 03.11.2017
Anwendungshinweis Robust Rear-View Camera (RVC) App Report 13.09.2017
Anwendungshinweis Optimization of GPU-Based Surround View on TI’s TDA2x SoC 12.09.2017
Anwendungshinweis Using DSS Write-Back Pipeline for RGB-to-YUV Conversion on DRA7xx Devices 14.08.2017
Anwendungshinweis Software Guidelines to EMIF/DDR3 Configuration on DRA7xx Devices 12.07.2017
Whitepaper Revolutionize the automotive cockpit 02.06.2017
Anwendungshinweis Linux Boot Time Optimizations on DRA7xx Devices 31.03.2017
Anwendungshinweis Interfacing DRA75x and DRA74x Audio to Analog Codecs (Rev. A) 17.02.2017
Anwendungshinweis Early Splash Screen on DRA7x Devices 31.01.2017
Anwendungshinweis Quality of Service (QoS) Knobs for DRA74x, DRA75x & TDA2x Family of Devices (Rev. A) 15.12.2016
Anwendungshinweis Gstreamer Migration Guidelines 26.04.2016
Benutzerhandbuch Jacinto6 Android Video Encoder Software Design Specification User's Guide 21.04.2016
Benutzerhandbuch Jacinto6 Android Video Decoder Software Design Specification User's Guide 21.04.2016
Anwendungshinweis Flashing Binaries to DRA7xx Factory Boards Using DFU 14.04.2016
Anwendungshinweis Tools and Techniques for Audio Debugging 13.04.2016
Anwendungshinweis Debugging Tools and Techniques With IPC3.x 30.03.2016
Technischer Artikel Infotainment for the Masses – Volkswagen MIB II Standard powered by TI PDF | HTML 17.02.2016
Benutzerhandbuch JAMR3 Tuner Application Board User’s Guide 09.02.2016
Anwendungshinweis Modifying Memory Usage for IPUMM Applications Loaded IPC 3.x for DRA75x, DRA74x (Rev. A) 15.01.2016
Technischer Artikel Difficult to see. Always in motion is the future PDF | HTML 04.01.2016
Technischer Artikel Securing the Scene PDF | HTML 16.12.2015
Whitepaper Informational ADAS as Software Upgrade to Today’s Infotainment Systems 14.10.2014
Product overview DRA75x “Jacinto 6 EP” and “Jacinto 6 Ex” Automotive Product Bulletin 25.09.2014
Anwendungshinweis Guide to fix Perf Issues Using QoS Knobs for DRA74x, DRA75x, TDA2x & TD3x Device 13.08.2014

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