DS25BR100

AKTIV

3,125-Gbps-LVDS-Puffer mit Übertragungs-Preemphasis und Empfangsentzerrung

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Datenblatt

document-pdfAcrobat DS25BR100/101 3.125Gbps LVDS Buffer w/Transmit Pre-Empha & Rcve Equalization datasheet (Rev. F) (Englisch)

DS25BR100

AKTIV

Datenblatt

Jetzt bestellen

Produktdetails

Function

Buffer, Equalizer

Protocols

CML, LVDS, LVPECL

Number of transmitters

1

Number of receivers

1

Signaling rate (Mbps)

3125

Input signal

CML, LVCMOS, LVDS, LVPECL

Output signal

LVDS

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Function

Buffer, Equalizer

Protocols

CML, LVDS, LVPECL

Number of transmitters

1

Number of receivers

1

Signaling rate (Mbps)

3125

Input signal

CML, LVCMOS, LVDS, LVPECL

Output signal

LVDS

Rating

Catalog

Operating temperature range (°C)

-40 to 85

WSON (NGQ)

8

9 mm² (3 mm × 3 mm)

DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation
Receive Equalization Reduces ISI Jitter Due to Media Loss
Transmit Pre-Emphasis Drives Lossy Backplanes and Cables
On-Chip 100Ω Input and Output Termination:
- Minimizes Insertion and Return Losses
- Reduces Component Count
- Minimizes Board Space
DS25BR101 Eliminates On-Chip Input Termination for Added Design Flexibility
7 kV ESD on LVDS I/O Pins Protects Adjoining Components
Small 3 mm x 3 mm WSON-8 Space Saving Package

All trademarks are the property of their respective owners.

DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation
Receive Equalization Reduces ISI Jitter Due to Media Loss
Transmit Pre-Emphasis Drives Lossy Backplanes and Cables
On-Chip 100Ω Input and Output Termination:
- Minimizes Insertion and Return Losses
- Reduces Component Count
- Minimizes Board Space
DS25BR101 Eliminates On-Chip Input Termination for Added Design Flexibility
7 kV ESD on LVDS I/O Pins Protects Adjoining Components
Small 3 mm x 3 mm WSON-8 Space Saving Package

All trademarks are the property of their respective owners.

The DS25BR100 and DS25BR101 are single channel 3.125 Gbps LVDS buffers optimized for high-speed signal transmission over lossy FR-4 printed circuit board backplanes and balanced metallic cables. Fully differential signal paths ensure exceptional signal integrity and noise immunity.

The DS25BR100 and DS25BR101 feature transmit pre-emphasis (PE) and receive equalization (EQ), making them ideal for use as a repeater device. Other LVDS devices with similar IO characteristics include the following products. The DS25BR120 features four levels of pre-emphasis for use as an optimized driver device, while the DS25BR110 features four levels of equalization for use as an optimized receiver device. The DS25BR150 is a buffer/repeater with the lowest power consumption and does not feature transmit pre-emphasis nor receive equalization.

Wide input common mode range allows the receiver to accept signals with LVDS, CML and LVPECL levels; the output levels are LVDS. A very small package footprint requires minimal space on the board while the flow-through pinout allows easy board layout. On the DS25BR100 the differential input and output is internally terminated with a 100Ω resistor to lower return losses, reduce component count and further minimize board space. For added design flexibility the 100Ω input terminations on the DS25BR101 have been eliminated. This elimination enables a designer to adjust the termination for custom interconnect topologies and layout.

The DS25BR100 and DS25BR101 are single channel 3.125 Gbps LVDS buffers optimized for high-speed signal transmission over lossy FR-4 printed circuit board backplanes and balanced metallic cables. Fully differential signal paths ensure exceptional signal integrity and noise immunity.

The DS25BR100 and DS25BR101 feature transmit pre-emphasis (PE) and receive equalization (EQ), making them ideal for use as a repeater device. Other LVDS devices with similar IO characteristics include the following products. The DS25BR120 features four levels of pre-emphasis for use as an optimized driver device, while the DS25BR110 features four levels of equalization for use as an optimized receiver device. The DS25BR150 is a buffer/repeater with the lowest power consumption and does not feature transmit pre-emphasis nor receive equalization.

Wide input common mode range allows the receiver to accept signals with LVDS, CML and LVPECL levels; the output levels are LVDS. A very small package footprint requires minimal space on the board while the flow-through pinout allows easy board layout. On the DS25BR100 the differential input and output is internally terminated with a 100Ω resistor to lower return losses, reduce component count and further minimize board space. For added design flexibility the 100Ω input terminations on the DS25BR101 have been eliminated. This elimination enables a designer to adjust the termination for custom interconnect topologies and layout.

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Technische Dokumentation

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Top-Dokumentation	Typ	Titel	Datum
*	Datenblatt	DS25BR100/101 3.125Gbps LVDS Buffer w/Transmit Pre-Empha & Rcve Equalization datasheet (Rev. F)	14.04.2013
	Anwendungshinweis	LVDS Repeaters and Crosspoints Extend the Reach of FPD-Link II Interfaces (Rev. A)	29.04.2013
	Anwendungshinweis	AN-1957 LVDS Signal Conditioners Reduce Data-Dependent Jitter (Rev. A)	26.04.2013
	Benutzerhandbuch	SMA to RJ45 Adapter Board User Guide	26.01.2012
	Benutzerhandbuch	3.125 Gbps LVDS Buffers with Pre-emphasis and Equalization User Guide	25.01.2012

Design und Entwicklung

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Evaluierungsplatine

DS25BR100EVK — LVDS-Einkanalpuffer-Familie, 3,125 Gbps, mit Preemphasis beim Senden und Entzerrung beim Empfangen

The DS25BR100EVK is an evaluation kit designed for demonstrating performance of the 3.125 Gbps LVDS Single Channel Buffers with Transmit Pre-Emphasis (PE) and Receive Equalization (EQ) family (DS25BR100, DS25BR110 and DS25BR120). The evaluation kit provides all three devices on a single board and (...)

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