SN65LV1023A

AKTIV

10-1-LVDS-SerDes-Transmitter 100–660 Mbps

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Datenblatt

document-pdfAcrobat 10-MHz to 66-MHz, 10:1-LVDS Serializer/Deserializer datasheet (Rev. E) (Englisch)

SN65LV1023A

AKTIV

Datenblatt

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Produktdetails

Function

Serializer

Protocols

Channel-Link I

Signaling rate (Mbps)

660

Input signal

LVDS

Output signal

LVCMOS, LVTTL

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Function

Serializer

Protocols

Channel-Link I

Signaling rate (Mbps)

660

Input signal

LVDS

Output signal

LVCMOS, LVTTL

Rating

Catalog

Operating temperature range (°C)

-40 to 85

SSOP (DB)

28

79.56 mm² (10.2 mm × 7.8 mm)

VQFN (RHB)

32

25 mm² (5 mm × 5 mm)

100-Mbps to 660-Mbps Serial LVDS Data Payload Bandwidth at 10-MHz
to 66-MHz System Clock
Pin-Compatible Superset of DS92LV1023/DS92LV1224
Chipset (Serializer/Deserializer) Power Consumption <450 mW (Typ) at 66 MHz
Synchronization Mode for Faster Lock
Lock Indicator
No External Components Required for PLL
28-Pin SSOP and Space Saving 5 × 5 mm QFN Packages Available
Industrial Temperature Qualified,
T_A = −40°C to 85°C
Programmable Edge Trigger on Clock
Flow-Through Pinout for Easy PCB Layout
APPLICATIONS
- Wireless Base Station
- Backplane Interconnect
- DSLAM

100-Mbps to 660-Mbps Serial LVDS Data Payload Bandwidth at 10-MHz
to 66-MHz System Clock
Pin-Compatible Superset of DS92LV1023/DS92LV1224
Chipset (Serializer/Deserializer) Power Consumption <450 mW (Typ) at 66 MHz
Synchronization Mode for Faster Lock
Lock Indicator
No External Components Required for PLL
28-Pin SSOP and Space Saving 5 × 5 mm QFN Packages Available
Industrial Temperature Qualified,
T_A = −40°C to 85°C
Programmable Edge Trigger on Clock
Flow-Through Pinout for Easy PCB Layout
APPLICATIONS
- Wireless Base Station
- Backplane Interconnect
- DSLAM

The SN65LV1023A serializer and SN65LV1224B deserializer comprise a 10-bit serdes chipset designed to transmit and receive serial data over LVDS differential backplanes at equivalent parallel word rates from 10 MHz to 66 MHz. Including overhead, this translates into a serial data rate between 120-Mbps and 792-Mbps payload encoded throughput.

Upon power up, the chipset link can be initialized via a synchronization mode with internally generated SYNC patterns or the deserializer can be allowed to synchronize to random data. By using the synchronization mode, the deserializer establishes lock within specified, shorter time parameters.

The device can be entered into a power-down state when no data transfer is required. Alternatively, a mode is available to place the output pins in the high-impedance state without losing PLL lock.

The SN65LV1023A and SN65LV1224B are characterized for operation over ambient air temperature of –40°C to 85°C.

The SN65LV1023A serializer and SN65LV1224B deserializer comprise a 10-bit serdes chipset designed to transmit and receive serial data over LVDS differential backplanes at equivalent parallel word rates from 10 MHz to 66 MHz. Including overhead, this translates into a serial data rate between 120-Mbps and 792-Mbps payload encoded throughput.

Upon power up, the chipset link can be initialized via a synchronization mode with internally generated SYNC patterns or the deserializer can be allowed to synchronize to random data. By using the synchronization mode, the deserializer establishes lock within specified, shorter time parameters.

The device can be entered into a power-down state when no data transfer is required. Alternatively, a mode is available to place the output pins in the high-impedance state without losing PLL lock.

The SN65LV1023A and SN65LV1224B are characterized for operation over ambient air temperature of –40°C to 85°C.

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Top-Dokumentation	Typ	Titel	Datum
*	Datenblatt	10-MHz to 66-MHz, 10:1-LVDS Serializer/Deserializer datasheet (Rev. E)	07.12.2009
*	Errata	SN65LV1023A Sync Pattern Generation Logic Error	26.06.2003
	Anwendungshinweis	Applications of Low-Voltage Differential Signaling (LVDS) in LED Walls	29.10.2020
	Application brief	Migrating from DS92LV1021A/1212A 10-bit SerDes to SN65LV1023A/1224B	15.11.2018
	Benutzerhandbuch	10:1 Serializer/Deserializer Evaluation Board	20.11.2013

Design und Entwicklung

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SN65LV1023A IBIS Model

SLLM358.ZIP (31 KB) - IBIS-Modell

Unterstützte Produkte und Hardware

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Gehäuse	Pins	CAD-Symbole, Footprints und 3D-Modelle
SSOP (DB)	28	Ultra Librarian
VQFN (RHB)	32	Ultra Librarian

Es gelten die allgemeinen Geschäftsbedingungen von TI für Evaluierungsartikel.

SN65LV1023A

10-1-LVDS-SerDes-Transmitter 100–660 Mbps

SN65LV1023A

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