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Microcontroladores (MCU) y procesadores
Microprocesadores y DSP
SoC del procesador de señal digital (DSP) de radar y audio

66AK2E05

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66AK2E05

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Detalles del producto

CPU 4 Arm Cortex-A15 Frequency (MHz) 1250, 1400 Coprocessors C66x DSP Protocols Ethernet PCIe 4 PCIe Gen 2 Hardware accelerators Packet Accelerator, Security Accelerator Features Networking Operating system Linux, RTOS Security Cryptographic acceleration, Device attestation & anti-counterfeit, Secure boot Rating Catalog Operating temperature range (°C) -40 to 100
CPU 4 Arm Cortex-A15 Frequency (MHz) 1250, 1400 Coprocessors C66x DSP Protocols Ethernet PCIe 4 PCIe Gen 2 Hardware accelerators Packet Accelerator, Security Accelerator Features Networking Operating system Linux, RTOS Security Cryptographic acceleration, Device attestation & anti-counterfeit, Secure boot Rating Catalog Operating temperature range (°C) -40 to 100
FCBGA (ABD) 1089 729 mm² (27 mm × 27 mm)
  • ARM® Cortex®-A15 MPCore™
    CorePac
    • Up to Four ARM Cortex-A15 Processor Cores at
      up to 1.4-GHz
    • 4MB L2 Cache Memory Shared by all Cortex-
      A15 Processor Cores
    • Full Implementation of ARMv7-A Architecture
      Instruction Set
    • 32KB L1 Instruction and Data Caches per Core
    • AMBA 4.0 AXI Coherency Extension (ACE)
      Master Port, Connected to MSMC (Multicore
      Shared Memory Controller) for Low Latency
      Access to SRAM and DDR3
  • One TMS320C66x DSP Core Subsystem (C66x
    CorePacs), Each With
    • 1.4 GHz C66x Fixed/Floating-Point DSP Core
      • 38.4 GMacs/Core for Fixed Point @ 1.2 GHz
      • 19.2 GFlops/Core for Floating Point @
        1.2 GHz
    • Memory
      • 32K Byte L1P Per CorePac
      • 32K Byte L1D Per CorePac
      • 512K Byte Local L2 Per CorePac
  • Multicore Shared Memory Controller (MSMC)
    • 2 MB SRAM Memory Shared by DSP CorePacs
      and ARM CorePac
    • Memory Protection Unit for Both SRAM and
      DDR3_EMIF
  • Multicore Navigator
    • 8k Multi-Purpose Hardware Queues with Queue
      Manager
    • One Packet-Based DMA Engine for Zero-
      Overhead Transfers
  • Network Coprocessor
    • Packet Accelerator Enables Support for
      • Transport Plane IPsec, GTP-U, SCTP,
        PDCP
      • L2 User Plane PDCP (RoHC, Air Ciphering)
      • 1 Gbps Wire Speed Throughput at 1.5
        MPackets Per Second
    • Security Accelerator Engine Enables Support for
      • IPSec, SRTP, 3GPP and WiMAX
        Air Interface, and SSL/TLS Security
      • ECB, CBC, CTR, F8, A5/3, CCM, GCM,
        HMAC, CMAC, GMAC, AES, DES, 3DES,
        Kasumi, SNOW 3G, SHA-1, SHA-2 (256-bit
        Hash), MD5
      • Up to 6.4 Gbps IPSec and 3 Gbps Air
        Ciphering
    • Ethernet Subsystem
      • Eight SGMII Ports with Wire Rate Switching
      • IEEE1588 v2 (with Annex D/E/F) Support
      • 8 Gbps Total Ingress/Egress Ethernet BW
        from Core
      • Audio/Video Bridging (802.1Qav/D6.0)
      • QOS Capability
      • DSCP Priority Mapping
  • Peripherals
    • Two PCIe Gen2 Controllers with Support for
      • Two Lanes per Controller
      • Supports Up to 5 GBaud
    • One HyperLink
      • Supports Connections to Other KeyStone
        Architecture Devices Providing Resource
        Scalability
      • Supports Up to 50 GBaud
    • 10-Gigabit Ethernet (10-GbE) Switch Subsystem
      • Two SGMII/XFI Ports with Wire Rate
        Switching and MACSEC Support
      • IEEE1588 v2 (with Annex D/E/F) Support
    • One 72-Bit DDR3/DDR3L Interface with Speeds
      Up to 1600 MTPS in DDR3 Mode
    • EMIF16 Interface
    • Two USB 2.0/3.0 Controllers
    • USIM Interface
    • Two UART Interfaces
    • Three I2C Interfaces
    • 32 GPIO Pins
    • Three SPI Interfaces
    • One TSIP
      • Support 1024 DS0s
      • Support 2 Lanes at 32.768/16.3848.192
        Mbps Per Lane
  • System Resources
    • Three On-Chip PLLs
    • SmartReflex Automatic Voltage Scaling
    • Semaphore Module
    • Thirteen 64-Bit Timers
    • Five Enhanced Direct Memory Access (EDMA)
      Modules
  • Commercial Case Temperature:
    • 0°C to 85°C
  • Extended Case Temperature:
    • –40°C to 100°C
  • ARM® Cortex®-A15 MPCore™
    CorePac
    • Up to Four ARM Cortex-A15 Processor Cores at
      up to 1.4-GHz
    • 4MB L2 Cache Memory Shared by all Cortex-
      A15 Processor Cores
    • Full Implementation of ARMv7-A Architecture
      Instruction Set
    • 32KB L1 Instruction and Data Caches per Core
    • AMBA 4.0 AXI Coherency Extension (ACE)
      Master Port, Connected to MSMC (Multicore
      Shared Memory Controller) for Low Latency
      Access to SRAM and DDR3
  • One TMS320C66x DSP Core Subsystem (C66x
    CorePacs), Each With
    • 1.4 GHz C66x Fixed/Floating-Point DSP Core
      • 38.4 GMacs/Core for Fixed Point @ 1.2 GHz
      • 19.2 GFlops/Core for Floating Point @
        1.2 GHz
    • Memory
      • 32K Byte L1P Per CorePac
      • 32K Byte L1D Per CorePac
      • 512K Byte Local L2 Per CorePac
  • Multicore Shared Memory Controller (MSMC)
    • 2 MB SRAM Memory Shared by DSP CorePacs
      and ARM CorePac
    • Memory Protection Unit for Both SRAM and
      DDR3_EMIF
  • Multicore Navigator
    • 8k Multi-Purpose Hardware Queues with Queue
      Manager
    • One Packet-Based DMA Engine for Zero-
      Overhead Transfers
  • Network Coprocessor
    • Packet Accelerator Enables Support for
      • Transport Plane IPsec, GTP-U, SCTP,
        PDCP
      • L2 User Plane PDCP (RoHC, Air Ciphering)
      • 1 Gbps Wire Speed Throughput at 1.5
        MPackets Per Second
    • Security Accelerator Engine Enables Support for
      • IPSec, SRTP, 3GPP and WiMAX
        Air Interface, and SSL/TLS Security
      • ECB, CBC, CTR, F8, A5/3, CCM, GCM,
        HMAC, CMAC, GMAC, AES, DES, 3DES,
        Kasumi, SNOW 3G, SHA-1, SHA-2 (256-bit
        Hash), MD5
      • Up to 6.4 Gbps IPSec and 3 Gbps Air
        Ciphering
    • Ethernet Subsystem
      • Eight SGMII Ports with Wire Rate Switching
      • IEEE1588 v2 (with Annex D/E/F) Support
      • 8 Gbps Total Ingress/Egress Ethernet BW
        from Core
      • Audio/Video Bridging (802.1Qav/D6.0)
      • QOS Capability
      • DSCP Priority Mapping
  • Peripherals
    • Two PCIe Gen2 Controllers with Support for
      • Two Lanes per Controller
      • Supports Up to 5 GBaud
    • One HyperLink
      • Supports Connections to Other KeyStone
        Architecture Devices Providing Resource
        Scalability
      • Supports Up to 50 GBaud
    • 10-Gigabit Ethernet (10-GbE) Switch Subsystem
      • Two SGMII/XFI Ports with Wire Rate
        Switching and MACSEC Support
      • IEEE1588 v2 (with Annex D/E/F) Support
    • One 72-Bit DDR3/DDR3L Interface with Speeds
      Up to 1600 MTPS in DDR3 Mode
    • EMIF16 Interface
    • Two USB 2.0/3.0 Controllers
    • USIM Interface
    • Two UART Interfaces
    • Three I2C Interfaces
    • 32 GPIO Pins
    • Three SPI Interfaces
    • One TSIP
      • Support 1024 DS0s
      • Support 2 Lanes at 32.768/16.3848.192
        Mbps Per Lane
  • System Resources
    • Three On-Chip PLLs
    • SmartReflex Automatic Voltage Scaling
    • Semaphore Module
    • Thirteen 64-Bit Timers
    • Five Enhanced Direct Memory Access (EDMA)
      Modules
  • Commercial Case Temperature:
    • 0°C to 85°C
  • Extended Case Temperature:
    • –40°C to 100°C

The 66AK2E0x is a high performance device based on TI’s KeyStone II Multicore SoC Architecture, incorporating the most performance-optimized Cortex-A15 processor single-core or quad-core CorePac and C66x DSP core, that can run at a core speed of up to 1.4 GHz. TI’s 66AK2E0x device enables a high performance, power-efficient and easy to use platform for developers of a broad range of applications such as enterprise grade networking end equipment, data center networking, avionics and defense, medical imaging, test and automation.

TI’s KeyStone II Architecture provides a programmable platform integrating various subsystems (for example, ARM CorePac (Cortex-A15 Processor Quad Core CorePac), C66x CorePac, network processing, and uses a queue-based communication system that allows the device resources to operate efficiently and seamlessly. This unique device architecture also includes a TeraNet switch that enables the wide mix of system elements, from programmable cores to high-speed IO, to each operate at maximum efficiency with no blocking or stalling.

TI’s C66x core launches a new era of DSP technology by combining fixed-point and floating point computational capability in the processor without sacrificing speed, size, or power consumption. The raw computational performance is an industry-leading 38.4 GMACS/core and 19.2 Gflops/core (@ 1.2 GHz operating frequency). It can execute 8 single precision floating point MAC operations per cycle and can perform double- and mixed-precision operations and is IEEE754 compliant. For fixed-point use, the C66x core has 4× the multiply accumulate (MAC) capability of C64×+ cores. The C66x CorePac incorporates 90 new instructions targeted for floating point and vector math oriented processing. These enhancements yield sizeable performance improvements in popular DSP kernels used in signal processing, mathematical, and image acquisition functions. The C66x core is backwards code compatible with TI'’s previous generation C6000 fixed and floating point DSP cores, ensuring software portability and shortened software development cycles for applications migrating to faster hardware.

The 66AK2E0x KeyStone II device integrates a large amount of on-chip memory. The Cortex-A15 processor cores each have 32KB of L1Data and 32KB of L1 Instruction cache. The up to four Cortex A15 cores in the ARM CorePac share a 4MB L2 Cache. In the DSP CorePac, in addition to 32KB of L1 program and 32KB of L1 data cache, there is 512KB of dedicated memory per core that can be configured as cache or as memory mapped RAM. The device also integrates 2MB of Multicore Shared Memory (MSMC) that can be used as a shared L3 SRAM. All L2 and MSMC memories incorporate error detection and error correction. For fast access to external memory, this device includes a 64-bit DDR-3 (72-bit with ECC support) external memory interface (EMIF) running at 1600 MTPS.

The device enables developers to use a variety of development and debugging tools that include GNU GCC, GDB, Open source Linux, Eclipse based debugging environment enabling kernel and user space debugging using a variety of Eclipse plug-ins including TI's industry leading IDE Code Composer Studio.

The 66AK2E0x is a high performance device based on TI’s KeyStone II Multicore SoC Architecture, incorporating the most performance-optimized Cortex-A15 processor single-core or quad-core CorePac and C66x DSP core, that can run at a core speed of up to 1.4 GHz. TI’s 66AK2E0x device enables a high performance, power-efficient and easy to use platform for developers of a broad range of applications such as enterprise grade networking end equipment, data center networking, avionics and defense, medical imaging, test and automation.

TI’s KeyStone II Architecture provides a programmable platform integrating various subsystems (for example, ARM CorePac (Cortex-A15 Processor Quad Core CorePac), C66x CorePac, network processing, and uses a queue-based communication system that allows the device resources to operate efficiently and seamlessly. This unique device architecture also includes a TeraNet switch that enables the wide mix of system elements, from programmable cores to high-speed IO, to each operate at maximum efficiency with no blocking or stalling.

TI’s C66x core launches a new era of DSP technology by combining fixed-point and floating point computational capability in the processor without sacrificing speed, size, or power consumption. The raw computational performance is an industry-leading 38.4 GMACS/core and 19.2 Gflops/core (@ 1.2 GHz operating frequency). It can execute 8 single precision floating point MAC operations per cycle and can perform double- and mixed-precision operations and is IEEE754 compliant. For fixed-point use, the C66x core has 4× the multiply accumulate (MAC) capability of C64×+ cores. The C66x CorePac incorporates 90 new instructions targeted for floating point and vector math oriented processing. These enhancements yield sizeable performance improvements in popular DSP kernels used in signal processing, mathematical, and image acquisition functions. The C66x core is backwards code compatible with TI'’s previous generation C6000 fixed and floating point DSP cores, ensuring software portability and shortened software development cycles for applications migrating to faster hardware.

The 66AK2E0x KeyStone II device integrates a large amount of on-chip memory. The Cortex-A15 processor cores each have 32KB of L1Data and 32KB of L1 Instruction cache. The up to four Cortex A15 cores in the ARM CorePac share a 4MB L2 Cache. In the DSP CorePac, in addition to 32KB of L1 program and 32KB of L1 data cache, there is 512KB of dedicated memory per core that can be configured as cache or as memory mapped RAM. The device also integrates 2MB of Multicore Shared Memory (MSMC) that can be used as a shared L3 SRAM. All L2 and MSMC memories incorporate error detection and error correction. For fast access to external memory, this device includes a 64-bit DDR-3 (72-bit with ECC support) external memory interface (EMIF) running at 1600 MTPS.

The device enables developers to use a variety of development and debugging tools that include GNU GCC, GDB, Open source Linux, Eclipse based debugging environment enabling kernel and user space debugging using a variety of Eclipse plug-ins including TI's industry leading IDE Code Composer Studio.
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Documentación técnica

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Documentación principal Tipo Título Opciones de formato Descargar la versión más reciente en inglés Fecha
* Hoja de datos 66AK2E05/02 Multicore DSP+ARM KeyStone II System-on-Chip (SoC) datasheet (Rev. D) 11/03/2015
* Errata 66AK2E05/02 KeyStone SoC Silicon Errata (Silicon Rev 1.0) (Rev. B) 20/08/2015
Guía del usuario ARM Assembly Language Tools v20.2.0.LTS User's Guide (Rev. Z) PDF | HTML 30/03/2023
Guía del usuario ARM Optimizing C/C++ Compiler v20.2.0.LTS User's Guide (Rev. W) PDF | HTML 30/03/2023
Nota sobre la aplicación DDR3 Design Requirements for KeyStone Devices (Rev. D) PDF | HTML 7/07/2022
Nota sobre la aplicación Keystone Error Detection and Correction EDC ECC (Rev. A) 25/06/2021
Nota sobre la aplicación How to Migrate CCS 3.x Projects to the Latest CCS (Rev. A) PDF | HTML 19/05/2021
Nota sobre la aplicación Using Arm ROM Bootloader on Keystone II Devices PDF | HTML 4/06/2019
Nota sobre la aplicación Keystone Multicore Device Family Schematic Checklist PDF | HTML 17/05/2019
Nota sobre la aplicación KeyStone II DDR3 interface bring-up PDF | HTML 7/03/2019
Informe POWERLINK on TI Sitara Processors (Rev. A) 10/01/2018
Guía del usuario KeyStone II Architecture Universal Serial Bus 3.0 (USB 3.0) (Rev. A) 21/08/2017
Nota sobre la aplicación Thermal Design Guide for DSP and Arm Application Processors (Rev. B) 14/08/2017
Guía del usuario Phase-Locked Loop (PLL) for KeyStone Devices User's Guide (Rev. I) 26/07/2017
Nota sobre la aplicación Power Consumption Summary for K2E System-on-Chip (SoC) Device Family 14/06/2017
Nota sobre la aplicación PCI Express (PCIe) Resource Wiki for Keystone Devices (Rev. A) 19/05/2017
Nota sobre la aplicación Processor SDK RTOS Audio Benchmark Starter Kit 12/04/2017
Nota sobre la aplicación Clocking Spreadsheet for K2E Device Family 26/01/2017
Guía del usuario Serializer/Deserializer (SerDes) for KeyStone II Devices User Guide (Rev. A) 27/07/2016
Nota sobre la aplicación Power Management of KS2 Device (Rev. C) 15/07/2016
Nota sobre la aplicación SERDES Link Commissioning on KeyStone I and II Devices 13/04/2016
Nota sobre la aplicación TI DSP Benchmarking PDF | HTML 13/01/2016
Nota sobre la aplicación Throughput Performance Guide for KeyStone II Devices (Rev. B) 22/12/2015
Nota sobre la aplicación Keystone II DDR3 Debug Guide 16/10/2015
Informe Making your search SIMPLE, even when your ideas are complex 10/08/2015
Informe Processing solutions for biometric systems 30/06/2015
Informe Quality of service on Keystone II architecture 7/05/2015
Guía del usuario Enhanced Direct memory Access 3 (EDMA3) for KeyStone Devices User's Guide (Rev. B) PDF | HTML 6/05/2015
Guía del usuario Gigabit Ethernet (GbE) Switch SS for K2E & K2L Devices User's Guide (Rev. A) 28/04/2015
Guía del usuario Multicore Navigator (CPPI) for KeyStone Architecture User's Guide (Rev. H) PDF | HTML 9/04/2015
Guía del usuario DDR3 Memory Controller for KeyStone II Devices User's Guide (Rev. C) 27/03/2015
Informe Save power and costs with TI's K2E on-chip networking features 25/03/2015
Nota sobre la aplicación Keystone II DDR3 Initialization 26/01/2015
Guía del usuario Power Sleep Controller (PSC) for KeyStone Devices User's Guide (Rev. C) 4/09/2014
Product overview 66AK2Ex KeyStone Multicore DSP+ARM(R) System-on-Chips (Rev. A) 3/09/2014
Informe KeyStone™-II-based processors: 10G Ethernet as an optical interface 25/08/2014
Guía del usuario Security Accelerator 2 (SA2) for K2E and K2L Devices User's Guide 19/08/2014
Guía del usuario Packet Accelerator 2 (PA2) for K2E and K2L Devices User's Guide 19/08/2014
Informe Differentiating AM5K2E02 and AM5K2E04 SoCs from Alternate ARM® Cortex®-A15 Devic 14/08/2014
Guía del usuario Network Coprocessor (NETCP) for K2E and K2L Devices User's Guide 13/08/2014
Nota sobre la aplicación Hardware Design Guide for KeyStone II Devices 24/03/2014
Product overview The Case for 10G Ethernet in Embedded Processing 13/11/2013
Guía del usuario PCI Express (PCIe) for KeyStone Devices User's Guide (Rev. D) 30/09/2013
Guía del usuario Debug and Trace for KeyStone II Devices User's Guide 26/07/2013
Guía del usuario ARM Bootloader User Guide for KeyStone II Devices 21/07/2013
Guía del usuario DSP Bootloader for KeyStone Architecture User's Guide (Rev. C) 15/07/2013
Guía del usuario Memory Protection Unit (MPU) for KeyStone Devices User's Guide (Rev. A) 28/06/2013
Guía del usuario C66x CorePac User's Guide (Rev. C) 28/06/2013
Guía del usuario HyperLink for KeyStone Devices User's Guide (Rev. C) 28/05/2013
Guía del usuario 10 Gigabit Ethernet Switch Subsystem User Guide for KeyStone II Devices 8/02/2013
Guía del usuario Multicore Shared Memory Controller (MSMC) User Guide for KeyStone II Devices 12/11/2012
Product overview Industrial Imaging: Applications of the K2H and K2E platforms 9/11/2012
Product overview Video Infrastructure - Applications of the K2E, K2H platforms 9/11/2012
Guía del usuario ARM CorePac User Guide for KeyStone II Devices 31/10/2012
Nota sobre la aplicación Multicore Programming Guide (Rev. B) 29/08/2012
Guía del usuario Serial Peripheral Interface (SPI) for KeyStone Devices User’s Guide (Rev. A) 30/03/2012
Guía del usuario Chip Interrupt Controller (CIC) for KeyStone Devices User's Guide (Rev. A) 27/03/2012
Guía del usuario 64-Bit Timer (Timer64) for KeyStone Devices User's Guide (Rev. A) 22/03/2012
Nota sobre la aplicación PCIe Use Cases for KeyStone Devices 13/12/2011
Nota sobre la aplicación Introduction to TMS320C6000 DSP Optimization 6/10/2011
Guía del usuario Inter-Integrated Circuit (I2C) for KeyStone Devices User's Guide 2/09/2011
Guía del usuario External Memory Interface (EMIF16) for KeyStone Devices User's Guide (Rev. A) 24/05/2011
Informe Software and Hardware Design Challenges Due to Dynamic Raw NAND Market 19/05/2011
Nota sobre la aplicación Optimizing Loops on the C66x DSP 9/11/2010
Guía del usuario General-Purpose Input/Output (GPIO) forKeyStone Devices User's Guide 9/11/2010
Guía del usuario C66x CPU and Instruction Set Reference Guide 9/11/2010
Nota sobre la aplicación Clocking Design Guide for KeyStone Devices 9/11/2010
Guía del usuario Universal Asynchronous Receiver/Transmitter (UART) for KeyStone Devices UG 9/11/2010
Guía del usuario C66x DSP Cache User's Guide 9/11/2010
Guía del usuario Telecom Serial Interface Port (TSIP) for KeyStone Devices User's Guide 9/11/2010

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Kit de desarrollo

EVMK2EX — Placa de desarrollo K2E

El EVMK2EX es una herramienta de desarrollo con todas las funciones para SoC basados en II 66AK2Exx y AM5K2Exx Keystone II. Comience hoy mismo a desarrollar sistemas informáticos integrados de uso general para aplicaciones industriales, de misión crítica y de red con esta placa de evaluación de (...)

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Sonda de depuración

TMDSEMU200-U — Sonda de depuración XDS200 USB

El XDS200 es una sonda de depuración (emulador) que se utiliza para depurar dispositivos integrados de TI. Para la mayoría de los dispositivos, se recomienda utilizar el XDS110 (www.ti.com/tool/TMDSEMU110-U), que es más nuevo y de menor costo. El XDS200 es compatible con una amplia variedad de (...)

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Sonda de depuración

TMDSEMU560V2STM-U — Sonda de depuración USB para rastreo del sistema con el software XDS560™ v2

El XDS560v2 es el modelo de mayor rendimiento de la familia de sondas de depuración XDS560™ y es compatible tanto con el estándar JTAG tradicional (IEEE 1149.1) como con cJTAG (IEEE 1149.7).  Tenga en cuenta que no es compatible con la depuración por cable serie (SWD).

Todas las sondas de (...)

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Sonda de depuración

TMDSEMU560V2STM-UE — Sonda de depuración USB y ethernet de seguimiento del sistema XDS560v2

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

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Kit de desarrollo de software (SDK)

BIOSLINUXMCSDK-K2 — MCSDK supporting SYS/BIOS RTOS and Linux OS for KeyStone II ARM A15 + DSP C66x

NOTE: K2x, C665x and C667x devices are now actively maintained on the Processor-SDK release stream. See links above.

Our Multicore Software Development Kits (MCSDK) provide highly-optimized bundles of foundational, platform-specific drivers to enable development on selected TI ARM and DSP devices. (...)

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Kit de desarrollo de software (SDK)

PROCESSOR-SDK-LINUX-K2E — Linux Processor SDK for K2E

 

El procesador de kit de desarrollo de software (SDK) es una plataforma de software unificada para procesadores integrados de TI que ofrece una configuración sencilla y un rápido acceso inmediato a pruebas de rendimiento y demostraciones.  Todas las versiones del SDK del procesador son coherentes (...)

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Kit de desarrollo de software (SDK)

PROCESSOR-SDK-LINUX-RT-K2E — Linux-RT Processor SDK for K2E

 

El procesador de kit de desarrollo de software (SDK) es una plataforma de software unificada para procesadores integrados de TI que ofrece una configuración sencilla y un rápido acceso inmediato a pruebas de rendimiento y demostraciones.  Todas las versiones del SDK del procesador son coherentes (...)

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Kit de desarrollo de software (SDK)

PROCESSOR-SDK-RTOS-K2E — RTOS Processor SDK for K2E

 

El procesador de kit de desarrollo de software (SDK) es una plataforma de software unificada para procesadores integrados de TI que ofrece una configuración sencilla y un rápido acceso inmediato a pruebas de rendimiento y demostraciones.  Todas las versiones del SDK del procesador son coherentes (...)

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Kit de desarrollo de software (SDK)

S2MEDDUS — Kits de herramientas de software (STK) para imágenes médicas

The TI Embedded Processor Software Toolkit for Medical Imaging (STK-MED) is a collection of several standard ultrasound and optical coherence tomography (OCT) algorithms for TI’s C66x™ and C64x+™ architecture. The algorithms showcase how medical imaging functions can leverage the C66x and (...)
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IDE, configuración, compilador o depurador

CCSTUDIO — Code Composer Studio™ integrated development environment (IDE)

El entorno de desarrollo integrado (IDE) CCStudio™ forma parte del amplio ecosistema de desarrollo CCStudio™ de TI y es un entorno de desarrollo integrado para los microcontroladores, procesadores, dispositivos de conectividad inalámbrica y sensores de radar de TI. El IDE CCStudio está disponible (...)

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Ejemplo de código o demostración

DEMOVIDEO-MULTICORE — Demostración de infraestructura de video multinúcleo para kit de desarrollo de software multinúcleo

This Multicore Video Infrastructure Demo package provides highly-optimized platform and video software components and enables development of real-time video applications on C66x multicore devices. The Multicore Video Infrastructure Demo gives developers the ability to evaluate performance and (...)

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Controlador o biblioteca

FFTLIB — Biblioteca FFT para dispositivos de punto flotante

The Texas Instruments FFT library is an optimized floating-point math function library for computing the discrete Fourier transform (DFT).

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MATHLIB — Biblioteca matemática DSP para dispositivos de punto flotante

The Texas Instruments math library is an optimized floating-point math function library for C programmers using TI floating point devices. These routines are typically used in computationally intensive real-time applications where optimal execution speed is critical. By using these routines instead (...)
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Controlador o biblioteca

SPRC264 — TMS320C5000/6000 Biblioteca de imágenes (IMGLIB)

La biblioteca de procesamiento de imágenes (IMGLIB) C5000/6000 es una biblioteca de funciones de procesamiento de imágenes o videos optimizada para programadores C. Incluye rutinas de procesamiento de imágenes/o videos de uso general invocables en C que se suelen utilizar en aplicaciones en tiempo (...)

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Controlador o biblioteca

SPRC265 — Biblioteca DSP TMS320C6000 (DSPLIB)

La biblioteca de procesadores de señales digitales (DSPLIB) TMS320C6000 es una biblioteca de funciones DSP optimizada para la plataforma para programadores C. Incluye rutinas de procesamiento de señales de uso general e invocables en C que se suelen utilizar en aplicaciones en tiempo real de gran (...)

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Códec de software

C66XCODECS — CÓDECS (video, voz) para dispositivos basados en C66x

TI codecs are free, come with production licensing and are available for download now. All are production-tested for easy integration into video and voice applications. In many cases, the C64x+ codecs are provided and validated for C66x platforms. Datasheets and Release Notes are on the download (...)

Productos y hardware compatibles
Modelo de simulación

66AK2E05 66AK2E02 ABD IBIS Model

SPRM611.ZIP (2180 KB) - Modelo IBIS
Productos y hardware compatibles
Modelo de simulación

66AK2E05 66AK2E02 ABD BSDL Model

SPRM612.ZIP (28 KB) - Modelo BSDL
Productos y hardware compatibles
Modelo de simulación

66AK2E05 66AK2E02 ABD Thermal Model

SPRM613.ZIP (5 KB) - Modelo térmico
Productos y hardware compatibles
Modelo de simulación

66AK2E05 and 66AK2E02 Power Consumption Model (Rev. A)

SPRM652A.ZIP (143 KB) - Modelo de potencia
Productos y hardware compatibles
Modelo de simulación

KeyStone II IBIS AMI Models

SPRM743.ZIP (265889 KB) - Modelo IBIS-AMI
lock = Requiere aprobación de exportación (1 minuto)
Productos y hardware compatibles
Diseño de referencia

TIDEP0026 — Diseño de referencia de generación de reloj K2E

A single clock source should not be used to drive multiple clock inputs for a high-performance processor device, such as multicore ARM Cortex-A15 based 66AK2Ex and AM5K2Ex processors, since excessive loading, reflections, and noise will negatively impact performance. These can be avoided through (...)

Productos y hardware compatibles
Diseño de referencia

TIDEP0031 — Secuenciación de potencia para K2E mediante UCD9090 con PMBus

The K2E devices require power supplies to be sequenced in a proper order. This design demonstrates power sequencing for the 66AK2Ex and AM5K2Ex families of KeyStone II ARM+DSP and ARM-only multicore processors by use of the UCD9090. The UCD9090 is a 10-rail PMBus/I2C addressable power-supply (...)

Productos y hardware compatibles
Diseño de referencia

TIDEP0041 — Diseño de referencia de generación de tensión de núcleo AVS SmartReflex, PMBus para K2E

The K2E requires the use of AVS SmartReflex control for the CVDD core voltage. This design provides method of generating the proper voltage without the need for any software. The circuit is currently implemented on the XEVMK2EX.

Productos y hardware compatibles
Diseño de referencia

TIDEP0042 — Diseño de referencia de generación de tensión de núcleo AVS SmartReflex para K2E con TPS544C25 y PMB

The K2E requires the use of AVS SmartReflex control for the CVDD core voltage. This design provides method of generating the proper voltage using software and the PMBus interface of the TPS544C25. The circuit can be implemented on the XEVMK2EX.

Productos y hardware compatibles
Encapsulado Pines Símbolos CAD, huellas y modelos 3D
FCBGA (ABD) 1089 Ultra Librarian
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