ADC12SJ1600

ACTIVO

ADC de un canal, 12 bits, 1,6 GSPS con interfaz JESD204C y generador de reloj de muestras integrado

Detalles del producto

Sample rate (max) (Msps) 1600 Resolution (bps) 12 Number of input channels 1 Interface type JESD204B, JESD204C Analog input BW (MHz) 6000 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 1000 Architecture Folding Interpolating SNR (dB) 57.4 ENOB (bit) 9 SFDR (dB) 66 Operating temperature range (°C) -40 to 85 Input buffer Yes
Sample rate (max) (Msps) 1600 Resolution (bps) 12 Number of input channels 1 Interface type JESD204B, JESD204C Analog input BW (MHz) 6000 Features Ultra High Speed Rating Catalog Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 1000 Architecture Folding Interpolating SNR (dB) 57.4 ENOB (bit) 9 SFDR (dB) 66 Operating temperature range (°C) -40 to 85 Input buffer Yes
FCCSP (AAV) 144 100 mm² 10 x 10
  • ADC Core:
    • Resolution: 12 Bit
    • Maximum sampling rate: 1.6GSPS
    • Non-interleaved architecture
    • Internal dither reduces high-order harmonics
  • Performance specifications (–1dBFS):
    • SNR (100MHz): 57.4dBFS
    • ENOB (100MHz): 9.1 Bits
    • SFDR (100MHz): 64dBc
    • Noise floor (–20dBFS): –147dBFS
  • Full-scale input voltage: 80mVPP-DIFF
  • Full-power input bandwidth: 6GHz
  • JESD204C Serial data interface:
    • Support for 2 to 8 (Quad, Dual channel) or 1 to 4 (Single channel) total SerDes lanes
    • Maximum baud-rate: 17.16Gbps
    • 64B/66B and 8B/10B encoding modes
    • Subclass-1 support for deterministic latency
    • Compatible with JESD204B receivers
  • Optional internal sampling clock generation
    • Internal PLL and VCO (7.2 to 8.2GHz)
  • SYSREF Windowing eases synchronization
  • Four clock outputs simplify system clocking
    • Reference clocks for FPGA or adjacent ADC
    • Reference clock for SerDes transceivers
  • Timestamp input and output for pulsed systems
  • Power consumption (1GSPS):
    • Quad Channel: 477mW/channel
    • Dual channel: 700mW/channel
    • Single channel: 1000mW
  • Power supplies: 1.1V, 1.9V
  • ADC Core:
    • Resolution: 12 Bit
    • Maximum sampling rate: 1.6GSPS
    • Non-interleaved architecture
    • Internal dither reduces high-order harmonics
  • Performance specifications (–1dBFS):
    • SNR (100MHz): 57.4dBFS
    • ENOB (100MHz): 9.1 Bits
    • SFDR (100MHz): 64dBc
    • Noise floor (–20dBFS): –147dBFS
  • Full-scale input voltage: 80mVPP-DIFF
  • Full-power input bandwidth: 6GHz
  • JESD204C Serial data interface:
    • Support for 2 to 8 (Quad, Dual channel) or 1 to 4 (Single channel) total SerDes lanes
    • Maximum baud-rate: 17.16Gbps
    • 64B/66B and 8B/10B encoding modes
    • Subclass-1 support for deterministic latency
    • Compatible with JESD204B receivers
  • Optional internal sampling clock generation
    • Internal PLL and VCO (7.2 to 8.2GHz)
  • SYSREF Windowing eases synchronization
  • Four clock outputs simplify system clocking
    • Reference clocks for FPGA or adjacent ADC
    • Reference clock for SerDes transceivers
  • Timestamp input and output for pulsed systems
  • Power consumption (1GSPS):
    • Quad Channel: 477mW/channel
    • Dual channel: 700mW/channel
    • Single channel: 1000mW
  • Power supplies: 1.1V, 1.9V

ADC12xJ1600 is a family of quad, dual and single channel, 12-bit, 1.6GSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 12-bit resolution makes the ADC12xJ1600 suited for a variety of multi-channel communications and test systems.

Full-power input bandwidth (−3dB) of 6GHz enables direct RF sampling of L-band and S-band.

A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems.

JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16Gbps, to allow the optimal configuration for each application.

ADC12xJ1600 is a family of quad, dual and single channel, 12-bit, 1.6GSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 12-bit resolution makes the ADC12xJ1600 suited for a variety of multi-channel communications and test systems.

Full-power input bandwidth (−3dB) of 6GHz enables direct RF sampling of L-band and S-band.

A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems.

JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16Gbps, to allow the optimal configuration for each application.

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* Data sheet ADC12xJ1600 Quad, Dual, or Single Channel 1.6GSPS, 12-Bit, Analog-to-Digital Converter (ADC) with JESD204C Interface datasheet (Rev. A) PDF | HTML 06 nov 2024

Diseño y desarrollo

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Placa de evaluación

ADC12QJ1600EVM — Módulo de evaluación de ADC12QJ1600 para ADC de 1,6 GSPS de cuatro canales y 12 bits con interfaz JE

El módulo de evaluación (EVM) ADC12QJ1600 permite evaluar el producto ADC12QJ1600-Q1. ADC12QJ1600-Q1 es un convertidor analógico a digital (ADC) de baja potencia, 12 bits, cuatro canales de 1.6 GSPS, que cuenta con una entrada analógica con búfer, un convertidor reductor con bucle de bloqueo de (...)

Guía del usuario: PDF
Placa de evaluación

TSW12QJ1600EVM — Módulo de evaluación ADC de interfaz de 8 canales (4 canales, dos sincronizados) de 12 bits 1.6 GSPS

The TSW12QJ1600 evaluation module (EVM) is used to evaluate the ADC12QJ1600-Q1 analog-to-digital converter (ADC) with different front-end options. ADC12QJ1600-Q1 is a 12-bit ADC capable of operating at sampling rates up to 1.6 gigasample per second (GSPS) with four analog input channels.

This design (...)

Guía del usuario: PDF
Modelo de simulación

ADC12QJ1600 IBIS-AMI Model

SBAM512.ZIP (68 KB) - IBIS-AMI Model
Herramienta de simulación

PSPICE-FOR-TI — PSpice® para herramienta de diseño y simulación de TI

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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FCCSP (AAV) 144 Ultra Librarian

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  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
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