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The ADS58B18/B19 are members of the ultralow power ADS4xxx analog-to-digital converter (ADC) family that features integrated analog buffers and SNRBoost technology. The ADS58B18 and ADS58B19 are 11-bit and 9-bit ADCs with sampling rates up to 200MSPS and 250MSPS, respectively. Innovative design techniques are used to achieve high dynamic performance while consuming extremely low power. The analog input pins have buffers with constant performance and input impedance across a wide frequency range. This architecture makes these parts well-suited for multi-carrier, wide bandwidth communications applications such as PA linearization.
The ADS58B18 uses TI-proprietary SNRBoost technology that can be used to overcome SNR limitation as a result of quantization noise for bandwidths less than Nyquist (fS/2).
Both devices have gain options that can be used to improve SFDR performance at lower full-scale input ranges, especially at very high input frequencies. They also include a dc offset correction loop that can be used to cancel the ADC offset. At lower sampling rates, the ADC automatically operates at scaled-down power with no loss in performance.
These devices support both double data rate (DDR) low-voltage differential signaling (LVDS) and parallel CMOS digital output interfaces. The low data rate of the DDR LVDS interface (maximum 500Mbps) makes it possible to use low-cost field-programmable gate array (FPGA)-based receivers. They have a low-swing LVDS mode that can be used to further reduce the power consumption. The strength of the LVDS output buffers can also be increased to support 50Ω differential termination.
The ADS58B18/B19 are both available in a compact QFN-48 package and specified over the industrial temperature range (–40°C to +85°C).
| Documentación principal | Tipo | Título | Opciones de formato | Fecha |
|---|---|---|---|---|
| * | Data sheet | 11-Bit, 200MSPS/9-Bit, 250MSPS, Ultralow-Power ADCs with Analog Buffer datasheet (Rev. D) | 28 ene 2011 | |
| User guide | Interfacing Altera FPGAs to ADS4249 and DAC3482 (TIDA-00069 Reference Guide) | 10 jul 2012 | ||
| Application note | High-Speed, Analog-to-Digital Converter Basics | 11 ene 2012 | ||
| Application note | Power Supply Design for the ADS41xx (Rev. A) | 29 dic 2011 | ||
| Application note | Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) | 10 sep 2010 | ||
| Application note | Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio | 28 abr 2009 | ||
| Application note | CDCE62005 as Clock Solution for High-Speed ADCs | 04 sep 2008 | ||
| Application note | CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters | 08 jun 2008 | ||
| Application note | Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 | 02 jun 2008 | ||
| Application note | QFN Layout Guidelines | 28 jul 2006 |
Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.
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The analog engineer’s calculator is designed to speed up many of the repetitive calculations that analog circuit design engineers use on a regular basis. This PC-based tool provides a graphical interface with a list of various common calculations ranging from setting operational-amplifier (...)
JITTER-SNR-CALC can be used for calculating theoretical Signal to Noise (SNR) performance of ADCs based on input frequency and clock jitter.
| Encapsulado | Pines | Símbolos CAD, huellas y modelos 3D |
|---|---|---|
| VQFN (RGZ) | 48 | Ultra Librarian |
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Analog Engineer's Calc Installer
General calculator tool for analog design support.
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