Inicio Lógica y traducción de voltaje Circuitos integrados de lógica de especialidades
Inicio
Lógica y traducción de voltaje
Circuitos integrados de lógica de especialidades

CD74HCT670

ACTIVO

Archivo de registro 4 por 4 CMOS Logic de alta velocidad

Haga su pedido ahora
Hoja de datos

CD74HCT670

ACTIVO
Hoja de datos Haga su pedido ahora

Detalles del producto

Technology family HCT Bits (#) 4 Rating Catalog Operating temperature range (°C) -55 to 125
Technology family HCT Bits (#) 4 Rating Catalog Operating temperature range (°C) -55 to 125
PDIP (N) 16 181.42 mm² 19.3 x 9.4 SOIC (D) 16 59.4 mm² 9.9 x 6
  • Simultaneous and Independent Read and Write Operations
  • Expandable to 512 Words of n-Bits
  • Three-State Outputs
  • Organized as 4 Words x 4 Bits Wide
  • Buffered Inputs
  • Typical Read Time = 16ns for ’HC670 VCC = 5V, CL = 15pF, TA = 25°C
  • Fanout (Over Temperature Range)
    • Standard Outputs...10 LSTTL Loads
    • Bus Driver Outputs...15 LSTTL Loads
  • Wide Operating Temperature Range... –55°C to 125°C
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • HC Types
    • 2V to 6V Operation
    • High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • HCT Types
    • 4.5V to 5.5V Operation
    • Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
    • CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
  • Simultaneous and Independent Read and Write Operations
  • Expandable to 512 Words of n-Bits
  • Three-State Outputs
  • Organized as 4 Words x 4 Bits Wide
  • Buffered Inputs
  • Typical Read Time = 16ns for ’HC670 VCC = 5V, CL = 15pF, TA = 25°C
  • Fanout (Over Temperature Range)
    • Standard Outputs...10 LSTTL Loads
    • Bus Driver Outputs...15 LSTTL Loads
  • Wide Operating Temperature Range... –55°C to 125°C
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • HC Types
    • 2V to 6V Operation
    • High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • HCT Types
    • 4.5V to 5.5V Operation
    • Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
    • CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH

The ’HC670 and CD74HCT670 are 16-bit register files organized as 4 words x 4 bits each. Read and write address and enable inputs allow simultaneous writing into one location while reading another. Four data inputs are provided to store the 4-bit word. The write address inputs (WA0 and WA1) determine the location of the stored word in the register. When write enable (WE\) is low the word is entered into the address location and it remains transparent to the data. The outputs will reflect the true form of the input data. When (WE\) is high data and address inputs are inhibited. Data acquisition from the four registers is made possible by the read address inputs (RA1 and RA0). The addressed word appears at the output when the read enable (RE\) is low. The output is in the high impedance state when the (RE\) is high. Outputs can be tied together to increase the word capacity to 512 x 4 bits.

The ’HC670 and CD74HCT670 are 16-bit register files organized as 4 words x 4 bits each. Read and write address and enable inputs allow simultaneous writing into one location while reading another. Four data inputs are provided to store the 4-bit word. The write address inputs (WA0 and WA1) determine the location of the stored word in the register. When write enable (WE\) is low the word is entered into the address location and it remains transparent to the data. The outputs will reflect the true form of the input data. When (WE\) is high data and address inputs are inhibited. Data acquisition from the four registers is made possible by the read address inputs (RA1 and RA0). The addressed word appears at the output when the read enable (RE\) is low. The output is in the high impedance state when the (RE\) is high. Outputs can be tied together to increase the word capacity to 512 x 4 bits.
open-in-new Buscar otro/a Circuitos integrados de lógica de especialidades
Descargar Ver vídeo con transcripción Video

Productos similares que pueden interesarle

open-in-new Comparar alternativas
Funcionalidad similar a la del dispositivo comparado
NUEVO SN74AHCT164 ACTIVO Registro de desplazamiento de carga en paralelo de 4.5 V a 5.5 V y 8 bits Voltage range (4.5V to 5.5V), average drive strength (8mA), average propagation delay (9ns)
SN74AHCT595 ACTIVO Registros de desplazamiento de 8 bits con registros de salida de 3 estados y entradas CMOS compatibl Larger voltage range (2V to 5.5V), shorter average propagation delay (9ns)

Documentación técnica

star =Principal documentación para este producto seleccionada por TI
No se encontraron resultados. Borre su búsqueda y vuelva a intentarlo.
Ver todo 13
Tipo Título Fecha
* Data sheet CD54HC670, CD74HC670, CD74HCT670 datasheet (Rev. C) 16 oct 2003
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 15 dic 2022
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 jul 2021
Selection guide Logic Guide (Rev. AB) 12 jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 dic 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 ene 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 jul 2004
User guide Signal Switch Data Book (Rev. A) 14 nov 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 ago 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 jun 1997
Application note Designing With Logic (Rev. C) 01 jun 1997
Application note SN54/74HCT CMOS Logic Family Applications and Restrictions 01 may 1996
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 01 abr 1996

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

14-24-LOGIC-EVM — Módulo de evaluación genérico de productos lógicos para encapsulados D, DB, DGV, DW, DYY, NS y PW de

El módulo de evaluación 14-24-LOGIC-EVM (EVM) está diseñado para admitir cualquier dispositivo lógico que esté en un encapsulado D, DW, DB, NS, PW, DYY o DGV de 14 a 24 pines.

Guía del usuario: PDF | HTML
No disponible en TI.com
Paquete Pasadores Descargar
PDIP (N) 16 Ver opciones
SOIC (D) 16 Ver opciones
Se aplican los Términos y condiciones estándar de TI para los elementos de evaluación.

Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

Soporte y capacitación

Foros de TI E2E™ con asistencia técnica de los ingenieros de TI

Ver todos los temas del foro en inglés

El contenido lo proporcionan “tal como está” TI y los colaboradores de la comunidad y no constituye especificaciones de TI. Consulte los términos de uso.

Si tiene preguntas sobre la calidad, el paquete o el pedido de productos de TI, consulte el soporte de TI. ​​​​​​​​​​​​​​

Videos