CDCE949

ACTIVO

Sintetizador de reloj VCXO programable de 4 PLL con salidas LVCMOS de 2,5 V o 3,3 V.

Detalles del producto

Number of outputs 9 Output type LVCMOS Output frequency (max) (MHz) 230 Core supply voltage (V) 1.8 Output supply voltage (V) 2.5, 3.3 Input type LVCMOS, XTAL Operating temperature range (°C) -40 to 85 Features Integrated EEPROM, Multiplier or divider, Spread-spectrum clocking (SSC) Rating Catalog
Number of outputs 9 Output type LVCMOS Output frequency (max) (MHz) 230 Core supply voltage (V) 1.8 Output supply voltage (V) 2.5, 3.3 Input type LVCMOS, XTAL Operating temperature range (°C) -40 to 85 Features Integrated EEPROM, Multiplier or divider, Spread-spectrum clocking (SSC) Rating Catalog
TSSOP (PW) 24 49.92 mm² (7.8 mm × 6.4 mm)
  • Member of programmable clock generator family
    • CDCEx913: 1 PLL, 3 outputs
    • CDCEx925: 2 PLLs, 5 outputs
    • CDCEx937: 3 PLLs, 7 outputs
    • CDCEx949: 4 PLLs, 9 outputs
  • In-system programmability and EEPROM
    • Serial programmable volatile register
    • Nonvolatile EEPROM to store customer settings
  • Flexible input clocking concept
    • External crystal: 8MHz to 32MHz
    • On-chip VCXO pull-range: ±150ppm
    • Single-ended LVCMOS up to 160MHz
  • Free selectable output frequency up to 230MHz
  • Low-noise PLL core
    • PLL loop filter components integrated
    • Low period jitter: 60ps (typical)
  • Separate output supply pins
    • CDCE949: 3.3V and 2.5V
    • CDCEL949: 1.8V
  • Flexible clock driver
    • Three user-definable control inputs [S0/S1/S2] (for example: SSC selection, frequency switching, output enable or power down)
    • Generates highly accurate clocks for video, audio, USB, IEEE1394, RFID, Bluetooth, WLAN, Ethernet™, and GPS
    • Generates common clock frequencies used with TI-DaVinci™, OMAP™, DSPs
    • Programmable SSC modulation
    • Enables 0ppm clock generation
  • 1.8V device core supply
  • Wide temperature range: –40°C to 85°C
  • Packaged in TSSOP
  • Development and programming kit for easy PLL design and programming (TI Pro-Clock™)
  • Member of programmable clock generator family
    • CDCEx913: 1 PLL, 3 outputs
    • CDCEx925: 2 PLLs, 5 outputs
    • CDCEx937: 3 PLLs, 7 outputs
    • CDCEx949: 4 PLLs, 9 outputs
  • In-system programmability and EEPROM
    • Serial programmable volatile register
    • Nonvolatile EEPROM to store customer settings
  • Flexible input clocking concept
    • External crystal: 8MHz to 32MHz
    • On-chip VCXO pull-range: ±150ppm
    • Single-ended LVCMOS up to 160MHz
  • Free selectable output frequency up to 230MHz
  • Low-noise PLL core
    • PLL loop filter components integrated
    • Low period jitter: 60ps (typical)
  • Separate output supply pins
    • CDCE949: 3.3V and 2.5V
    • CDCEL949: 1.8V
  • Flexible clock driver
    • Three user-definable control inputs [S0/S1/S2] (for example: SSC selection, frequency switching, output enable or power down)
    • Generates highly accurate clocks for video, audio, USB, IEEE1394, RFID, Bluetooth, WLAN, Ethernet™, and GPS
    • Generates common clock frequencies used with TI-DaVinci™, OMAP™, DSPs
    • Programmable SSC modulation
    • Enables 0ppm clock generation
  • 1.8V device core supply
  • Wide temperature range: –40°C to 85°C
  • Packaged in TSSOP
  • Development and programming kit for easy PLL design and programming (TI Pro-Clock™)

The CDCE949 and CDCEL949 are modular PLL-based low cost, high-performance, programmable clock synthesizers, multipliers, and dividers. These devices generate up to nine output clocks from a single input frequency. Each output is programmable in-system for any clock frequency up to 230MHz, using up to four independent configurable PLLs.

The CDCEx949 has separate output supply pins (VDDOUT): 1.8V for the CDCEL949 and 2.5V to 3.3V for the CDCE949.

The input accepts an external crystal or LVCMOS clock signal. If an external crystal is used, an on-chip load capacitor is adequate for most applications. The value of the load capacitor is programmable from 0pF to 20pF. Additionally, an on-chip VCXO is selectable, allowing synchronization of the output frequency to an external control signal, that is, a PWM signal.

The deep M/N divider ratio allows the generation of 0ppm audio or video, networking (WLAN, Bluetooth, Ethernet, GPS) or Interface (USB, IEEE1394, Memory Stick) clocks from a reference input frequency, such as 27MHz.

All PLLs support spread spectrum clocking (SSC). SSC can be center-spread or down-spread clocking. This is a common technique to reduce electromagnetic interference (EMI).

Based on the PLL frequency and the divider settings, the internal loop-filter components are automatically adjusted to achieve high stability, and to optimize the jitter-transfer characteristics of each PLL.

The device supports non-volatile EEPROM programming for easy customization of the device to the application. The CDCEx949 is preset to a factory-default configuration. The device can be reprogrammed to a different application configuration before PCB assembly, or reprogrammed by in-system programming. All device settings are programmable through the SDA and SCL bus, a 2-wire serial interface.

The CDCE949 and CDCEL949 are modular PLL-based low cost, high-performance, programmable clock synthesizers, multipliers, and dividers. These devices generate up to nine output clocks from a single input frequency. Each output is programmable in-system for any clock frequency up to 230MHz, using up to four independent configurable PLLs.

The CDCEx949 has separate output supply pins (VDDOUT): 1.8V for the CDCEL949 and 2.5V to 3.3V for the CDCE949.

The input accepts an external crystal or LVCMOS clock signal. If an external crystal is used, an on-chip load capacitor is adequate for most applications. The value of the load capacitor is programmable from 0pF to 20pF. Additionally, an on-chip VCXO is selectable, allowing synchronization of the output frequency to an external control signal, that is, a PWM signal.

The deep M/N divider ratio allows the generation of 0ppm audio or video, networking (WLAN, Bluetooth, Ethernet, GPS) or Interface (USB, IEEE1394, Memory Stick) clocks from a reference input frequency, such as 27MHz.

All PLLs support spread spectrum clocking (SSC). SSC can be center-spread or down-spread clocking. This is a common technique to reduce electromagnetic interference (EMI).

Based on the PLL frequency and the divider settings, the internal loop-filter components are automatically adjusted to achieve high stability, and to optimize the jitter-transfer characteristics of each PLL.

The device supports non-volatile EEPROM programming for easy customization of the device to the application. The CDCEx949 is preset to a factory-default configuration. The device can be reprogrammed to a different application configuration before PCB assembly, or reprogrammed by in-system programming. All device settings are programmable through the SDA and SCL bus, a 2-wire serial interface.

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Documentación técnica

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Documentación principal Tipo Título Opciones de formato Descargar la versión más reciente en inglés Fecha
* Hoja de datos CDCE(L)949: Flexible Low Power LVCMOS Clock Generator With SSC Support for EMI Reduction datasheet (Rev. H) PDF | HTML 23/07/2025
Artículo técnico The five benefits of multifaceted clocking devices PDF | HTML 17/05/2016
Nota sobre la aplicación VCXO Application Guideline for CDCE(L)9xx Family (Rev. A) 23/04/2012
Guía del usuario CDCE(L)9XX & CDCEx06 Programming Evaluation Module Manual (Rev. A) 22/11/2010
Guía del usuario CDCE(L)9xx Performance Evaluation Module (Rev. A) 7/07/2010
Nota sobre la aplicación General I2C / EEPROM usage for the CDCE(L)9xx family 26/01/2010
Nota sobre la aplicación Troubleshooting I2C Bus Protocol 19/10/2009
Nota sobre la aplicación Usage of I2C for CDCE(L)949, CDCE(L)937, CDCE(L)925, CDCE(L)913 23/09/2009
Nota sobre la aplicación Generating Low Phase-Noise Clocks for Audio Data Converters from Low Frequency 31/03/2008
Nota sobre la aplicación Practical consideration on choosing a crystal for CDCE(L)9xx family 24/03/2008
Nota sobre la aplicación Clocking Recommendations for DM6446 Digital Video EVM with Sngle PLL (Rev. A) 8/08/2007

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

CDCE949PERF-EVM — Módulo de evaluación del rendimiento de CDCE949

The CDCE949Perf-Evaluation Module will help to verify the functionality and performance of CDCE949 with the options of crystal and 1.8 V LVCMOS inputs. The outputs can be connected to the Oscilloscope directly with SMA cables. The below information/items can be included The EVM use’s (...)

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En inventario
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Placa de evaluación

CDCEL9XXPROGEVM — Placa de programación EEPROM de la familia CDCE(L)949

The clock generator CDCE(L)949 family has integrated EEPROM that allows the default frequency settings to be saved upon start up. CDCEL9XXPROGEVM is a programming board that allows a fast programming of prototyping samples or small production quantities. It applies to all 8 devices in the family: (...)

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En inventario
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Software de aplicación y estructura

SCAC097 — Executable File Without LabVIEW 8.2 Run Time Engine

Productos y hardware compatibles
Controlador o biblioteca

SCAC131 — Drivers for the CDCEL9xx programmer EVM

Productos y hardware compatibles
Soporte de software

CLOCKPRO — ClockPro Software

TI's ClockPro software allows users to program/configure the following devices in a friendly GUI interface:

  • CDCE949
  • CDCE937
  • CDCE925
  • CDCE913
  • CDCE906
  • CDCE706
  • CDCEL949
  • CDCEL937
  • CDCEL925
  • CDCEL913

It is intended to be used with the evaluation modules of the above devices.

Productos y hardware compatibles
Soporte de software

SCAC073 — TI-Pro-Clock Programming Software

Productos y hardware compatibles
Modelo de simulación

CDCE949 IBIS Model (Rev. B)

SCAC094B.ZIP (42 KB) - Modelo IBIS
Productos y hardware compatibles
Herramienta de diseño

CLOCK-TREE-ARCHITECT — Software de programación de diseño de árbol de reloj

La herramienta de síntesis de tipo árbol de reloj “arquitecto de tipo árbol de reloj” agiliza el proceso de diseño al generar soluciones de árbol de reloj en función de los requisitos del sistema. La herramienta extrae datos de una amplia base de datos de productos de relojes para generar una (...)

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Diseño de referencia

TIDA-010057 — Diseño de referencia de la fuente de alimentación de la sonda inteligente de ultrasonido

Los avances tecnológicos significativos y el alto grado de integración en las imágenes médicas, especialmente las sondas inteligentes de ultrasonido portátiles, están impulsando a los ingenieros a crear soluciones de energía de gran eficiencia e inmunes al ruido en un tamaño reducido. Este diseño (...)
Productos y hardware compatibles
Diseño de referencia

TIDA-010269 — Diseño de referencia de la fuente de alimentación para dispositivo de imágenes por ultrasonido portá

Este diseño de referencia se creó para alimentar la sonda de ultrasonido inteligente de 128 canales de última generación que adopta nuestro transmisor y receptor de nueva generación. El tamaño compacto (88 mm x 45 mm x 20 mm) incluye todas las funciones de alimentación para una sonda inteligente (...)
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Encapsulado Pines Símbolos CAD, huellas y modelos 3D
TSSOP (PW) 24 Ultra Librarian

Pedidos y calidad

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Soporte y capacitación

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