Inicio Interfaz Circuitos integrados LVDS, M-LVDS y PECL
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Circuitos integrados LVDS, M-LVDS y PECL

SN65LVP20

ACTIVO

Repetidor PECL a LVPECL de 4 Gbps

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SN65LVP20

ACTIVO
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Detalles del producto

Function Repeater, Translator Protocols LVPECL Number of transmitters 1 Number of receivers 1 Signaling rate (Mbps) 4000 Input signal Differential Output signal LVPECL Rating Catalog Operating temperature range (°C) -40 to 85
Function Repeater, Translator Protocols LVPECL Number of transmitters 1 Number of receivers 1 Signaling rate (Mbps) 4000 Input signal Differential Output signal LVPECL Rating Catalog Operating temperature range (°C) -40 to 85
WSON (DRF) 8 4 mm² (2 mm × 2 mm)
  • Low-Voltage PECL Input and Low-Voltage PECL or LVDS Outputs
  • Signaling Rates to 4 Gbps or Clock Rates to 2 GHz
    • 120-ps Output Transition Times
    • Less than 45 ps Total Jitter
    • Less than 630 ps Propagation Delay Times
  • 2.5-V or 3.3-V Supply Operation
  • 2-mm x 2-mm Small-Outline No-Lead Package
  • APPLICATIONS
    • PECL-to-LVDS Translation
    • Data or Clock Signal Amplification
  • Low-Voltage PECL Input and Low-Voltage PECL or LVDS Outputs
  • Signaling Rates to 4 Gbps or Clock Rates to 2 GHz
    • 120-ps Output Transition Times
    • Less than 45 ps Total Jitter
    • Less than 630 ps Propagation Delay Times
  • 2.5-V or 3.3-V Supply Operation
  • 2-mm x 2-mm Small-Outline No-Lead Package
  • APPLICATIONS
    • PECL-to-LVDS Translation
    • Data or Clock Signal Amplification

The SN65LVDS20 and SN65LVP20 are a high-speed differential receiver and driver connected as a repeater. The receiver accepts low-voltage positive-emitter-coupled logic (PECL) at signaling rates up to 4 Gbps and repeats it as either an LVDS or PECL output signal. The signal path through the device is differential for low radiated emissions and minimal added jitter.

The outputs of the SN65LVDS20 are LVDS levels as defined by TIA/EIA-644-A. The outputs of the SN65LVDP20 are compatible with low-voltage PECL levels. A low-level input to EN enables the outputs. A high-level input puts the output into a high-impedance state. Both outputs are designed to drive differential transmission lines with nominally 100- characteristic impedance.

Both devices provide a voltage reference (VBB) of typically 1.35 V below VCC for use in receiving single-ended PECL input signals. When not used, VBB should be unconnected or open.

All devices are characterized for operation from -40°C to 85°C.

The SN65LVDS20 and SN65LVP20 are a high-speed differential receiver and driver connected as a repeater. The receiver accepts low-voltage positive-emitter-coupled logic (PECL) at signaling rates up to 4 Gbps and repeats it as either an LVDS or PECL output signal. The signal path through the device is differential for low radiated emissions and minimal added jitter.

The outputs of the SN65LVDS20 are LVDS levels as defined by TIA/EIA-644-A. The outputs of the SN65LVDP20 are compatible with low-voltage PECL levels. A low-level input to EN enables the outputs. A high-level input puts the output into a high-impedance state. Both outputs are designed to drive differential transmission lines with nominally 100- characteristic impedance.

Both devices provide a voltage reference (VBB) of typically 1.35 V below VCC for use in receiving single-ended PECL input signals. When not used, VBB should be unconnected or open.

All devices are characterized for operation from -40°C to 85°C.
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Documentación técnica

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Documentación principal Tipo Título Opciones de formato Descargar la versión más reciente en inglés Fecha
* Hoja de datos LVPECL and LVS Repeater/Translator With Enable datasheet (Rev. A) 13/09/2005

Diseño y desarrollo

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Modelo de simulación

SN65LVP20 IBIS Model

SLLC223.ZIP (8 KB) - Modelo IBIS
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