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Microcontroladores (MCU) y procesadores
Microprocesadores y DSP
Sistemas automotrices SoC de asistencia al conductor

TDA4AEN-Q1

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SoC con Arm® Cortex®-A53 cuádruple, 4 TOPS de IA y C7xDSP para percepción y análisis de visión

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TDA4AEN-Q1

ACTIVO
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Detalles del producto

CPU 4 Arm Cortex-A53 Frequency (MHz) 1400 Coprocessors 1 Arm Cortex-R5F Display type 1 DSI, MIPI DPI, OLDI Protocols Ethernet, TSN PCIe 1 PCIe Gen 3 Hardware accelerators C7™ NPU, Deep learning accelerator, Depth and motion processing accelerator, Video decode accelerator, Video encode accelerator, Vision processing accelerator Features Vision Analytics Operating system AutoSAR, FreeRTOS, INTEGRITY, Linux, QNX, SafeRTOS, VxWorks, u-velOSity Security Secure boot TI functional safety category Functional Safety-Compliant Rating Automotive Power supply solution TPS65224-Q1 Operating temperature range (°C) -40 to 125 Edge AI enabled Edge AI Studio enabled, Yes
CPU 4 Arm Cortex-A53 Frequency (MHz) 1400 Coprocessors 1 Arm Cortex-R5F Display type 1 DSI, MIPI DPI, OLDI Protocols Ethernet, TSN PCIe 1 PCIe Gen 3 Hardware accelerators C7™ NPU, Deep learning accelerator, Depth and motion processing accelerator, Video decode accelerator, Video encode accelerator, Vision processing accelerator Features Vision Analytics Operating system AutoSAR, FreeRTOS, INTEGRITY, Linux, QNX, SafeRTOS, VxWorks, u-velOSity Security Secure boot TI functional safety category Functional Safety-Compliant Rating Automotive Power supply solution TPS65224-Q1 Operating temperature range (°C) -40 to 125 Edge AI enabled Edge AI Studio enabled, Yes
FCBGA (AMW) 594 324 mm² (18 mm × 18 mm)

Processor Cores:

  • Up to Quad 64-bit Arm Cortex-A53 microprocessor subsystem at up to 1.4GHz
    • Quad-core Cortex-A53 cluster with 512KB L2 shared cache with SECDED ECC
    • Each A53 core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection
  • Single-core Arm Cortex-R5F at up to 800MHz, integrated as part of MCU Channel with FFI
    • 32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories
    • 512KB SRAM with SECDED ECC
  • Single-core Arm Cortex-R5F at up to 800MHz, integrated to support Device Management
    • 32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories
  • Single-core Arm Cortex-R5F at up to 800MHz, integrated to support Run-time Management
    • 32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories
  • Two Deep Learning Accelerators (up to 4 TOPS total), each with:
    • C7x floating point, up to 40 GFLOPS, 256-bit Vector DSP at up to 1.0GHz
    • Matrix Multiply Accelerator (MMA), up to 2 TOPS (8b) at up to 1.0GHz
    • 64KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection
    • 2.25MB of L2 SRAM with SECDED ECC
  • Depth and Motion Processing Accelerators (DMPAC)
    • Dense Optical Flow (DOF) Accelerator
    • Stereo Disparity Engine (SDE) Accelerator
  • Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators:
    • 600 MP/s ISP
    • Support for 12-bit RGB-IR
    • Support for up to 16-bit input RAW format
    • Line support up to 4096
    • Wide Dynamic Range (WDR), Lens Distortion Correction (LDC), Vision Imaging Subsystem (VISS), and Multi-Scalar (MSC) support
      • Output color format : 8-bits, 12-bits, and YUV 4:2:2, YUV 4:2:0, RGB, HSV/HSL

Multimedia:

  • Display subsystem
    • Triple display support over OLDI/LVDS (1x OLDI-DL, 1x or 2x OLDI-SL), DSI or DPI
      • OLDI-SL (Single Link): up to 1920 x 1080 at 60fps (165-MHz Pixel Clock)
      • OLDI-DL (Dual Link): up to 3840 x 1080 at 60fps (150-MHz Pixel Clock)
      • MIPI DSI: with 4 Lane MIPI® D-PHY supports up to 3840 x 1080 at 60fps (300-MHz Pixel Clock)
      • DPI (24-bit RGB parallel interface): up to 1920 x 1080 at 60fps (165-MHz pixel clock)
    • Four display pipelines with hardware overlay support. A maximum of two display pipelines may be used per display.
    • Supports safety features such as freeze frame detection and data correctness check
  • 3D Graphics Processing Unit (TDA4VEN)
    • IMG BXS-4-64 with 256KB cache
    • Up to 50 GFLOPS
    • Single shader core
    • OpenGL ES3.2 and Vulkan 1.2 API support
  • Four Camera Serial Interface (CSI-2) Receiver with 4 Lane D-PHY
    • MIPI® CSI-2 v1.3 Compliant + MIPI® D-PHY 1.2
    • CSI-RX supports for 1,2,3, or 4 data lane mode up to 2.5Gbps per lane
    • CSI-TX supports for 1,2, or 4 data lane mode up to 2.5Gbps per lane
  • One CSI2.0 Transmitter with 4 Lane D-PHY (shared with MIPI DSI)
  • Video Encoder/Decoder
    • Support for HEVC (H.265) Main profiles at Level 5.1 High-tier
    • Support for H.264 BaseLine/Main/High Profiles at Level 5.2
    • Support for up to 4K UHD resolution (3840 × 2160)
      • Up to 500 MP/s decode/encode support (4K60)
  • Motion JPEG encode at 416MPixels/s withresolutions up to 4K UHD (3840 × 2160)

Memory Subsystem:

  • On-chip RAM dedicated to key processing cores
    • 256KB of On-Chip RAM (OCRAM) with SECDED ECC
    • 256KB of On-Chip RAM with SECDED ECC in SMS Subsystem
    • 512KB of On-chip RAM with SECDED ECC in Cortex-R5F MCU Subsystem
    • 64KB of On-chip RAM with SECDED ECC in R5F Device Manager Subsystem
    • 64KB of On-chip RAM with SECDED ECC in R5F Run-time Manager Subsystem
    • 2.25MB of L2 SRAM with SECDED ECC in each C7x Deep Learning Accelerator (up to 4.5MB total)
  • DDR Subsystem (DDRSS)
    • Supports LPDDR4 memory types
    • 32-bit data bus with inline ECC
    • Supports speeds up to 4000 MT/s
    • Max LPDDR4 size of 8GB

Functional Safety:

  • Functional Safety-Compliant targeted for Automotive (on select part numbers)
    • Developed for functional safety applications
    • Documentation will be available to aid ISO 26262 functional safety system design
    • Systematic capability up to ASIL D targeted
    • Hardware integrity up to ASIL B targeted
    • Safety-related certification
      • ISO 26262 planned
  • AEC - Q100 qualified

Security:

  • Secure boot supported
    • Hardware-enforced Root-of-Trust (RoT)
    • Support to switch RoT via backup key
    • Support for takeover protection, IP protection, and anti-roll back protection
  • Trusted Execution Environment (TEE) supported
    • Arm TrustZone based TEE
    • Extensive firewall support for isolation
    • Secure watchdog/timer/IPC
    • Secure storage support
    • Replay Protected Memory Block (RPMB) support
  • Dedicated Security Controller with user programmable HSM core and dedicated security DMA & IPC subsystem for isolated processing
  • Cryptographic acceleration supported
    • Session-aware cryptographic engine with ability to auto-switch key-material based on incoming data stream
  • Supports cryptographic cores
    • AES – 128-/192-/256-Bit key sizes
    • SHA2 – 224-/256-/384-/512-Bit key sizes
    • DRBG with true random number generator
    • PKA (Public Key Accelerator) to Assist in RSA/ECC processing for secure boot
  • Debugging security
    • Secure software controlled debug access
    • Security aware debugging

High-Speed Interfaces:

  • PCI-Express Gen3 single lane controller (PCIE)
    • Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3 (8.0GT/s) operation with auto-negotiation
  • Integrated Ethernet switch supporting (total 2 external ports)
    • RMII(10/100) or RGMII (10/100/1000) or SGMII (1Gbps)
    • IEEE1588 (Annex D, Annex E, Annex F with 802.1AS PTP)
    • Clause 45 MDIO PHY management
    • Packet Classifier based on ALE engine with 512 classifiers
    • Priority based flow control
    • Time Sensitive Networking (TSN) support
    • Four CPU H/W interrupt Pacing
    • IP/UDP/TCP checksum offload in hardware
  • USB3.1-Gen1 Port
    • One enhanced SuperSpeed Gen1 port
    • Port configurable as USB host, USB peripheral, or USB Dual-Role Device
    • Integrated USB VBUS detection
  • USB2.0 Port
    • Port configurable as USB host, USB peripheral, or USB Dual-Role Device (DRD mode)
    • Integrated USB VBUS detection

General Connectivity and Automotive interfaces:

  • 9x Universal Asynchronous Receiver-Transmitters (UART)
  • 5x Serial Peripheral Interface (SPI) controllers
  • 7x Inter-Integrated Circuit (I2C) ports
  • 5x Multichannel Audio Serial Ports (McASP)
  • General-Purpose I/O (GPIO), All LVCMOS I/O can be configured as GPIO
  • 4x Controller Area Network (CAN) modules with CAN-FD support

Media and Data Storage:

  • 3x Secure Digital (SD) (4b+4b+8b) interfaces
    • 1x 8-bit eMMC interface up to HS400 speed
    • 2x 4-bit SD/SDIO interfaces up to UHS-I
    • Compliant with eMMC 5.1, SD 3.0, and SDIO Version 3.0
  • 1× General-Purpose Memory Controller (GPMC) up to 133MHz
  • OSPI/QSPI with DDR / SDR support
    • Support for Serial NAND and Serial NOR Flash
    • 4GBytes memory address support
    • XIP mode with optional on-the-fly encryption

Technology / Package:

  • 16-nm FinFET technology
  • 18 mm x 18 mm, 0.65-mm pitch with VCA, 594-pin FCBGA (AMW)

Companion Power Management Solution:

  • Functional Safety-Compliant support up to ASIL-B or SIL-2 targeted
  • TPS6522x PMIC
  • TPS6287x Stackable, Fast Transient Bucks

Processor Cores:

  • Up to Quad 64-bit Arm Cortex-A53 microprocessor subsystem at up to 1.4GHz
    • Quad-core Cortex-A53 cluster with 512KB L2 shared cache with SECDED ECC
    • Each A53 core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection
  • Single-core Arm Cortex-R5F at up to 800MHz, integrated as part of MCU Channel with FFI
    • 32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories
    • 512KB SRAM with SECDED ECC
  • Single-core Arm Cortex-R5F at up to 800MHz, integrated to support Device Management
    • 32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories
  • Single-core Arm Cortex-R5F at up to 800MHz, integrated to support Run-time Management
    • 32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories
  • Two Deep Learning Accelerators (up to 4 TOPS total), each with:
    • C7x floating point, up to 40 GFLOPS, 256-bit Vector DSP at up to 1.0GHz
    • Matrix Multiply Accelerator (MMA), up to 2 TOPS (8b) at up to 1.0GHz
    • 64KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection
    • 2.25MB of L2 SRAM with SECDED ECC
  • Depth and Motion Processing Accelerators (DMPAC)
    • Dense Optical Flow (DOF) Accelerator
    • Stereo Disparity Engine (SDE) Accelerator
  • Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators:
    • 600 MP/s ISP
    • Support for 12-bit RGB-IR
    • Support for up to 16-bit input RAW format
    • Line support up to 4096
    • Wide Dynamic Range (WDR), Lens Distortion Correction (LDC), Vision Imaging Subsystem (VISS), and Multi-Scalar (MSC) support
      • Output color format : 8-bits, 12-bits, and YUV 4:2:2, YUV 4:2:0, RGB, HSV/HSL

Multimedia:

  • Display subsystem
    • Triple display support over OLDI/LVDS (1x OLDI-DL, 1x or 2x OLDI-SL), DSI or DPI
      • OLDI-SL (Single Link): up to 1920 x 1080 at 60fps (165-MHz Pixel Clock)
      • OLDI-DL (Dual Link): up to 3840 x 1080 at 60fps (150-MHz Pixel Clock)
      • MIPI DSI: with 4 Lane MIPI® D-PHY supports up to 3840 x 1080 at 60fps (300-MHz Pixel Clock)
      • DPI (24-bit RGB parallel interface): up to 1920 x 1080 at 60fps (165-MHz pixel clock)
    • Four display pipelines with hardware overlay support. A maximum of two display pipelines may be used per display.
    • Supports safety features such as freeze frame detection and data correctness check
  • 3D Graphics Processing Unit (TDA4VEN)
    • IMG BXS-4-64 with 256KB cache
    • Up to 50 GFLOPS
    • Single shader core
    • OpenGL ES3.2 and Vulkan 1.2 API support
  • Four Camera Serial Interface (CSI-2) Receiver with 4 Lane D-PHY
    • MIPI® CSI-2 v1.3 Compliant + MIPI® D-PHY 1.2
    • CSI-RX supports for 1,2,3, or 4 data lane mode up to 2.5Gbps per lane
    • CSI-TX supports for 1,2, or 4 data lane mode up to 2.5Gbps per lane
  • One CSI2.0 Transmitter with 4 Lane D-PHY (shared with MIPI DSI)
  • Video Encoder/Decoder
    • Support for HEVC (H.265) Main profiles at Level 5.1 High-tier
    • Support for H.264 BaseLine/Main/High Profiles at Level 5.2
    • Support for up to 4K UHD resolution (3840 × 2160)
      • Up to 500 MP/s decode/encode support (4K60)
  • Motion JPEG encode at 416MPixels/s withresolutions up to 4K UHD (3840 × 2160)

Memory Subsystem:

  • On-chip RAM dedicated to key processing cores
    • 256KB of On-Chip RAM (OCRAM) with SECDED ECC
    • 256KB of On-Chip RAM with SECDED ECC in SMS Subsystem
    • 512KB of On-chip RAM with SECDED ECC in Cortex-R5F MCU Subsystem
    • 64KB of On-chip RAM with SECDED ECC in R5F Device Manager Subsystem
    • 64KB of On-chip RAM with SECDED ECC in R5F Run-time Manager Subsystem
    • 2.25MB of L2 SRAM with SECDED ECC in each C7x Deep Learning Accelerator (up to 4.5MB total)
  • DDR Subsystem (DDRSS)
    • Supports LPDDR4 memory types
    • 32-bit data bus with inline ECC
    • Supports speeds up to 4000 MT/s
    • Max LPDDR4 size of 8GB

Functional Safety:

  • Functional Safety-Compliant targeted for Automotive (on select part numbers)
    • Developed for functional safety applications
    • Documentation will be available to aid ISO 26262 functional safety system design
    • Systematic capability up to ASIL D targeted
    • Hardware integrity up to ASIL B targeted
    • Safety-related certification
      • ISO 26262 planned
  • AEC - Q100 qualified

Security:

  • Secure boot supported
    • Hardware-enforced Root-of-Trust (RoT)
    • Support to switch RoT via backup key
    • Support for takeover protection, IP protection, and anti-roll back protection
  • Trusted Execution Environment (TEE) supported
    • Arm TrustZone based TEE
    • Extensive firewall support for isolation
    • Secure watchdog/timer/IPC
    • Secure storage support
    • Replay Protected Memory Block (RPMB) support
  • Dedicated Security Controller with user programmable HSM core and dedicated security DMA & IPC subsystem for isolated processing
  • Cryptographic acceleration supported
    • Session-aware cryptographic engine with ability to auto-switch key-material based on incoming data stream
  • Supports cryptographic cores
    • AES – 128-/192-/256-Bit key sizes
    • SHA2 – 224-/256-/384-/512-Bit key sizes
    • DRBG with true random number generator
    • PKA (Public Key Accelerator) to Assist in RSA/ECC processing for secure boot
  • Debugging security
    • Secure software controlled debug access
    • Security aware debugging

High-Speed Interfaces:

  • PCI-Express Gen3 single lane controller (PCIE)
    • Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3 (8.0GT/s) operation with auto-negotiation
  • Integrated Ethernet switch supporting (total 2 external ports)
    • RMII(10/100) or RGMII (10/100/1000) or SGMII (1Gbps)
    • IEEE1588 (Annex D, Annex E, Annex F with 802.1AS PTP)
    • Clause 45 MDIO PHY management
    • Packet Classifier based on ALE engine with 512 classifiers
    • Priority based flow control
    • Time Sensitive Networking (TSN) support
    • Four CPU H/W interrupt Pacing
    • IP/UDP/TCP checksum offload in hardware
  • USB3.1-Gen1 Port
    • One enhanced SuperSpeed Gen1 port
    • Port configurable as USB host, USB peripheral, or USB Dual-Role Device
    • Integrated USB VBUS detection
  • USB2.0 Port
    • Port configurable as USB host, USB peripheral, or USB Dual-Role Device (DRD mode)
    • Integrated USB VBUS detection

General Connectivity and Automotive interfaces:

  • 9x Universal Asynchronous Receiver-Transmitters (UART)
  • 5x Serial Peripheral Interface (SPI) controllers
  • 7x Inter-Integrated Circuit (I2C) ports
  • 5x Multichannel Audio Serial Ports (McASP)
  • General-Purpose I/O (GPIO), All LVCMOS I/O can be configured as GPIO
  • 4x Controller Area Network (CAN) modules with CAN-FD support

Media and Data Storage:

  • 3x Secure Digital (SD) (4b+4b+8b) interfaces
    • 1x 8-bit eMMC interface up to HS400 speed
    • 2x 4-bit SD/SDIO interfaces up to UHS-I
    • Compliant with eMMC 5.1, SD 3.0, and SDIO Version 3.0
  • 1× General-Purpose Memory Controller (GPMC) up to 133MHz
  • OSPI/QSPI with DDR / SDR support
    • Support for Serial NAND and Serial NOR Flash
    • 4GBytes memory address support
    • XIP mode with optional on-the-fly encryption

Technology / Package:

  • 16-nm FinFET technology
  • 18 mm x 18 mm, 0.65-mm pitch with VCA, 594-pin FCBGA (AMW)

Companion Power Management Solution:

  • Functional Safety-Compliant support up to ASIL-B or SIL-2 targeted
  • TPS6522x PMIC
  • TPS6287x Stackable, Fast Transient Bucks

The TDA4VEN/TDA4AEN (aka, TDA4-Entry) processor family is an extension of the Jacinto™ 7 automotive-grade family of heterogeneous Arm® processors targeted at Advanced Driver Assistance System (ADAS) applications. With embedded Deep Learning (DL), Video, Vision Processing, and 3D Graphics acceleration, display interface and extensive automotive peripheral and networking options, TDA4VEN/TDA4AEN is built for a set of cost and power sensitive automotive applications such as NCAP front camera or entry-level park assistance systems. The cost optimized TDA4VEN/TDA4AEN provides an optimized performance compute for both traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced automotive platforms supporting multiple sensor modalities in stand-alone Electronic Control Units (ECUs).

TDA4VEN/TDA4AEN contains up to four Arm® Cortex®-A53 cores with 64-bit architecture, a Vision Processing Accelerator (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators, Deep Learning (DL), Dense Optical Flow (DOF) video and 3D Graphics accelerators, a Cortex®-R5F MCU Island core and two Cortex®-R5F cores for Device and Run-time Management. The Cortex-A53s provide the powerful computing elements necessary for Linux applications as well as the implementation of traditional vision computing based algorithms. Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader sensor suite including RGB-InfraRed (RGB-IR), support for higher bit depth, and features targeting analytics applications. Key cores include TI’s Dense Optical Flow (DOF) accelerator as well two “C7x” next generation DSP with scalar and vector cores, dedicated “MMA” deep learning accelerator combined with a large 2.25MB L2 memory enabling performance up to 4 TOPS within the lowest power envelope in the industry when operating at the typical automotive worst case junction temperature of 125°C.

TDA4VEN/TDA4AEN integrates high-speed IOs including a PCIe Gen-3 (1L) and 3-port Gigabit Ethernet switch with one internal port and two external ports with TSN support. In addition, an extensive peripherals set is included in TDA4VEN/TDA4AEN to enable system level connectivity such as USB, MMC/SD, four CSI2.0 Camera interface, OSPI, CAN-FD and GPMC for parallel host interface to an external ASIC/FPGA. TDA4VEN/TDA4AEN supports secure boot for IP protection with the built-in HSM (Hardware Security Module) and employs advanced power management support for power-sensitive applications. Integrated diagnostics and safety features support operations up to ASIL-B at SoC level, (ASIL-D systematic level).

The TDA4VEN/TDA4AEN (aka, TDA4-Entry) processor family is an extension of the Jacinto™ 7 automotive-grade family of heterogeneous Arm® processors targeted at Advanced Driver Assistance System (ADAS) applications. With embedded Deep Learning (DL), Video, Vision Processing, and 3D Graphics acceleration, display interface and extensive automotive peripheral and networking options, TDA4VEN/TDA4AEN is built for a set of cost and power sensitive automotive applications such as NCAP front camera or entry-level park assistance systems. The cost optimized TDA4VEN/TDA4AEN provides an optimized performance compute for both traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced automotive platforms supporting multiple sensor modalities in stand-alone Electronic Control Units (ECUs).

TDA4VEN/TDA4AEN contains up to four Arm® Cortex®-A53 cores with 64-bit architecture, a Vision Processing Accelerator (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators, Deep Learning (DL), Dense Optical Flow (DOF) video and 3D Graphics accelerators, a Cortex®-R5F MCU Island core and two Cortex®-R5F cores for Device and Run-time Management. The Cortex-A53s provide the powerful computing elements necessary for Linux applications as well as the implementation of traditional vision computing based algorithms. Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader sensor suite including RGB-InfraRed (RGB-IR), support for higher bit depth, and features targeting analytics applications. Key cores include TI’s Dense Optical Flow (DOF) accelerator as well two “C7x” next generation DSP with scalar and vector cores, dedicated “MMA” deep learning accelerator combined with a large 2.25MB L2 memory enabling performance up to 4 TOPS within the lowest power envelope in the industry when operating at the typical automotive worst case junction temperature of 125°C.

TDA4VEN/TDA4AEN integrates high-speed IOs including a PCIe Gen-3 (1L) and 3-port Gigabit Ethernet switch with one internal port and two external ports with TSN support. In addition, an extensive peripherals set is included in TDA4VEN/TDA4AEN to enable system level connectivity such as USB, MMC/SD, four CSI2.0 Camera interface, OSPI, CAN-FD and GPMC for parallel host interface to an external ASIC/FPGA. TDA4VEN/TDA4AEN supports secure boot for IP protection with the built-in HSM (Hardware Security Module) and employs advanced power management support for power-sensitive applications. Integrated diagnostics and safety features support operations up to ASIL-B at SoC level, (ASIL-D systematic level).
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Documentación técnica

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Documentación principal Tipo Título Opciones de formato Descargar la versión más reciente en inglés Fecha
* Hoja de datos TDA4VEN, TDA4AEN Jacinto™ Processors datasheet (Rev. B) PDF | HTML 26/03/2026
* Guía del usuario J722S TDA4VEN TDA4AEN AM67 Processor Silicon Revision 1.0 Technical Reference Manual (Rev. C) PDF | HTML 23/11/2025
* Errata J722S TDA4VEN TDA4AEN AM67 Processor Silicon Revision 1.0 Errata (Rev. A) PDF | HTML 15/04/2025
Product overview TIDLRunner: Simplifying the 'Bring Your Own Model' Development Flow for Edge AI Accelerated Processors PDF | HTML 14/05/2026
Informe Securing the Future: Cyber Resilience Act (EU-CRA) Compliance with TI’s Jacinto and Sitara Processors PDF | HTML 24/04/2026
Información sobre seguridad funcional J721E, J721S2, J7200, J784S4, and J742S2 TÜV SÜD Letter of Confirmation for Software Component Qualification 1/10/2025
Información sobre seguridad funcional J7200, J721E, J721S2, J722S, J742S2, and J784S4 SDL TÜV SÜD Functional Safety Certificate (Rev. A) 25/09/2025
Información sobre seguridad funcional TÜV SÜD Certificate for Functional Safety Software Development Process (Rev. D) 17/06/2025
Nota sobre la aplicación Building a Driver and Occupancy Monitoring System with an RGB-IR Camera (Rev. A) PDF | HTML 20/03/2025
Nota sobre la aplicación MCAN Debug Guide PDF | HTML 18/02/2025
Nota sobre la aplicación Microcontroller Abstraction Layer on Jacinto™ and Sitara™ Embedded Processors PDF | HTML 28/01/2025
Guía del usuario J722S/TDA4VEN/TDA4AEN/AM67 Power Estimation Tool User’s Guide (Rev. A) PDF | HTML 3/10/2024
Nota sobre la aplicación Jacinto 7 LPDDR4 Board Design and Layout Guidelines (Rev. F) PDF | HTML 5/08/2024
Nota sobre la aplicación Debugging GPU Driver Issues on TDA4x and AM6x Devices PDF | HTML 20/06/2024
Nota sobre la aplicación Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design Guidelines (Rev. A) PDF | HTML 4/06/2024
Product overview J722S/AM67x/TDA4VEN/TDA4AEN Processor Automotive Power Designs using TPS6522312-Q1 PMIC PDF | HTML 18/04/2024
Nota sobre la aplicación Jacinto7 AM6x/TDA4x/DRA8x Schematic Checklist (Rev. B) PDF | HTML 4/04/2024
Nota sobre la aplicación Jacinto7 HS Device Customer Return Process PDF | HTML 16/11/2023
Informe Designing an Efficient Edge AI System with Highly Integrated Processors (Rev. A) PDF | HTML 13/03/2023
Nota sobre la aplicación UART Log Debug System on Jacinto 7 SoC PDF | HTML 9/01/2023
Product overview Jacinto™ 7 Safety Product Overview PDF | HTML 15/08/2022
Nota sobre la aplicación Dual-TDA4x System Solution PDF | HTML 29/04/2022
Nota sobre la aplicación SPI Enablement & Validation on TDA4 Family PDF | HTML 5/04/2022
Artículo técnico How are sensors and processors creating more intelligent and autonomous robots? PDF | HTML 29/03/2022
Artículo técnico How to simplify your embedded edge AI application development PDF | HTML 28/01/2022
Nota sobre la aplicación Enabling MAC2MAC Feature on Jacinto7 Soc 10/01/2022
Información sobre seguridad funcional Leverage Jacinto 7 Processors Functional Safety Features for Automotive Designs (Rev. A) PDF | HTML 13/10/2021
Nota sobre la aplicación TDA4 Flashing Techniques PDF | HTML 8/07/2021
Informe Security Enablers on Jacinto™ 7 Processors 4/01/2021
Informe Enabling Differentiation through MCU Integration on Jacinto™ 7 Processors 22/10/2020
Nota sobre la aplicación OSPI Tuning Procedure PDF | HTML 8/07/2020

Diseño y desarrollo

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Placa de evaluación

J722SXH01EVM — Módulo de evaluación TDA4VEN, TDA4AEN y AM67

El módulo de evaluación del kit de inicio J722SXH01EVM se basa en nuestro procesador de visión y visualización J722S, TDA4VEN y TDA4AEN y AM67, que incluye rendimiento Arm® Cortex®-A53 escalable, procesador de señal de imagen con soporte de hasta 600 MP/s, acelerador de IA de hasta 4 (...)

Guía del usuario: PDF | HTML
Productos y hardware compatibles
En inventario
Límite:
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No disponible
Sonda de depuración

TMDSEMU110-U — Sonda de depuración XDS110 JTAG

El XDS110 de Texas Instruments es una nueva clase de sonda de depuración (emulador) para procesadores integrados de TI. El XDS110 sustituye a la familia XDS100, al tiempo que es compatible con una mayor variedad de estándares (IEEE1149.1, IEEE1149.7, SWD) en un único pod. Todas las sondas de (...)

Productos y hardware compatibles
En inventario
Límite:
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No disponible
Sonda de depuración

LB-3P-TRACE32-ARM — Sistema de depuración y seguimiento Lauterbach TRACE32 para microcontroladores y procesadores basado

Lauterbach‘s TRACE32® tools are a suite of leading-edge hardware and software components that enables developers to analyze, optimize and certify all kinds of Arm®-based microcontrollers and processors. The globally renowned debug and trace solutions for embedded systems and SoCs are the perfect (...)

Desde: Lauterbach GmbH
Productos y hardware compatibles
Sonda de depuración

TSK-3P-BLUEBOX — TASKING BlueBox hardware debugger

TASKING’s Debug, Trace, and Test tools offer comprehensive solutions for efficient debugging, tracing, and testing of TI's embedded systems. The scalable TASKING BlueBox debuggers allow users to easily flash, debug, and test across TI's portfolio. Development on TI hardware is made even easier with (...)

Desde: TASKING Germany GmbH
Productos y hardware compatibles
Kit de desarrollo de software (SDK)

PROCESSOR-SDK-LINUX-J722S — Processor SDK Linux for J722S

El kit de desarrollo de software (SDK) del procesador J722S para sistemas operativos en tiempo real (RTOS) se puede utilizar junto con el SDK del procesador para Linux® o el SDK del procesador para QNX® a fin de formar una plataforma de desarrollo de software con múltiples procesadores para los (...)

Productos y hardware compatibles
Kit de desarrollo de software (SDK)

PROCESSOR-SDK-QNX-J722S — Processor SDK QNX for J722S

El kit de desarrollo de software (SDK) del procesador J722S para sistemas operativos en tiempo real (RTOS) se puede utilizar junto con el SDK del procesador para Linux® o el SDK del procesador para QNX® a fin de formar una plataforma de desarrollo de software con múltiples procesadores para los (...)

Productos y hardware compatibles
Kit de desarrollo de software (SDK)

PROCESSOR-SDK-RTOS-J722S — Processor SDK RTOS for J722S

El kit de desarrollo de software (SDK) del procesador J722S para sistemas operativos en tiempo real (RTOS) se puede utilizar junto con el SDK del procesador para Linux® o el SDK del procesador para QNX® a fin de formar una plataforma de desarrollo de software con múltiples procesadores para los (...)

Productos y hardware compatibles
IDE, configuración, compilador o depurador

CCSTUDIO — Code Composer Studio™ integrated development environment (IDE)

CCStudio™ IDE is part of TI's extensive CCStudio™ development ecosystem and is an integrated development environment for TI's microcontrollers, processors, wireless connectivity devices, and radar sensors. CCStudio IDE is available as desktop or cloud-based applications. The cloud version (...)

Productos y hardware compatibles
IDE, configuración, compilador o depurador

DDR-CONFIG-J722S — Herramienta de configuración DDR

This SysConfig based tool simplifies the process of configuring the DDR Subsystem Controller and PHY to interface to SDRAM devices. Based on the memory device, board design, and topology the tool outputs files to initialize and train the selected memory.
Productos y hardware compatibles
IDE, configuración, compilador o depurador

SYSCONFIG — Standalone desktop version of SysConfig

CCStudio™ SysConfig is part of TI's extensive CCStudio™ development ecosystem and is a configuration tool that simplifies hardware and software configuration challenges to accelerate software development.

SysConfig provides an intuitive graphical user interface for configuring pins, peripherals, (...)

Productos y hardware compatibles
IDE, configuración, compilador o depurador

TSK-3P-VX-TOOLSET — VX-TOOLSET de TASKING para Arm

VX-TOOLSET para Arm es una cadena de herramientas de compilación certificada para el desarrollo de software integrado de seguridad crítica en dispositivos seleccionados con núcleos Cortex-M y Cortex-R. Gracias a la integración con Eclipse IDE, la compatibilidad avanzada con multinúcleo y el (...)

Desde: TASKING Germany GmbH
Productos y hardware compatibles
Sistema operativo (SO)

GHS-INTEGRITY-RTOS — Green Hills INTEGRITY RTOS

The flagship of Green Hills Software operating systems—the INTEGRITY RTOS—is built around a partitioning architecture to provide embedded systems with total reliability, absolute security, and maximum real-time performance. With its leadership pedigree underscored by certifications in a (...)
Productos y hardware compatibles
Sistema operativo (SO)

GHS-3P-UVELOSITY — Green Hills Software u-velOSity Safety RTOS

The µ-velOSity™ Safety RTOS is the smallest of Green Hills Software's real-time operating systems and was designed especially for microcontrollers. It supports a wide range of TI processor families using the Arm® Cortex-M or Cortex-R cores as a main CPU or as a co-processors (...)

Desde: Green Hills Software
Productos y hardware compatibles
Sistema operativo (SO)

WHIS-3P-SAFERTOS — RTOS de seguridad precertificado SAFERTOS de WITTENSTEIN

SAFERTOS® es un sistema operativo único en tiempo real diseñado para procesadores integrados. Está precertificado según las normas IEC 61508 SIL3 e ISO 26262 ASILD por TÜV SÜD. SAFERTOS® se diseñó específicamente para la seguridad por el equipo de expertos de WHIS y se usa globalmente en (...)

Desde: WITTENSTEIN High Integrity Systems
Productos y hardware compatibles
Software de aplicación y estructura

PAI-3P-PHANTOMVISION — Software de visión Phantom AI que se ejecuta en procesadores Jacinto para aplicaciones de automoción

PhantomVision™ is a scalable, flexible and reliable deep learning based computer vision solution that provides a comprehensive suite of Euro NCAP compliant ADAS features. It is a visual perception engine that enables a single or multiple cameras to autonomously recognize road objects and (...)

Desde: Phantom AI
Productos y hardware compatibles
Firmware

USIT-3P-SECIC-HSM — Firmware Uni-Sentry SecIC-HSM

El SecIC-HSM está diseñado para cumplir con los requisitos de ciberseguridad necesarios para los chips MCU/SoC. El firmware HSM se puede aplicar en campos como automóviles, nuevas energías, fotovoltaica, robótica, salud y aviación. Las funciones de ciberseguridad proporcionadas disponibles incluyen (...)

Desde: Shanghai Uni-Sentry Intelligent Technology Co., LTD
Productos y hardware compatibles
Firmware

USIT-3P-SECIC-PQC — Firmware de algoritmos Uni-Sentry SecIC-PQC

Las soluciones de seguridad de Uni-Sentry adoptan algoritmos PQC capaces de resistir las amenazas de descifrado planteadas por los ordenadores cuánticos a los algoritmos criptográficos tradicionales. El firmware del PQC está cooptimizado con el Módulo de Seguridad de Hardware (HSM), aprovechando la (...)

Desde: Shanghai Uni-Sentry Intelligent Technology Co., LTD
Productos y hardware compatibles
Soporte de software

EXLFR-3P-ESYNC-OTA — Actualizaciones inalámbricas de OTA Excelfore esync para vehículos definidos por software

Experience the future of the connected SDV starting with full vehicle OTA from Excelfore. The standardized and structured eSync pipeline securely scales to reach all the ECUs and smart sensors in the car, with the flexibility to cover any in-vehicle network topology or system architecture.
eSync (...)

Desde: ExcelFore
Productos y hardware compatibles
Modelo de simulación

J722S BSDL Model

SPRM854.ZIP (12 KB) - Modelo BSDL
Productos y hardware compatibles
Modelo de simulación

J722S IBIS Model

SPRM855.ZIP (4140 KB) - Modelo IBIS
Productos y hardware compatibles
Modelo de simulación

J722S Thermal Model

SPRM856.ZIP (0 KB) - Modelo térmico
Productos y hardware compatibles
Encapsulado Pines Símbolos CAD, huellas y modelos 3D
FCBGA (AMW) 594 Ultra Librarian
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