GUI para el módulo de evaluación (EVM)
TLK10002
Transceptor de velocidad múltiple de 10 Gbps de doble canal
Hoja de datos
TLK10002
- Dual-Channel, 10-Gbps, Multi-Rate Transceiver
- Supports All CPRI and OBSAI Data Rates From 1 Gbps to 10 Gbps
- Integrated Latency Measurement Function, Accuracy up to 814 ps
- Supports SERDES Operation With up to 10-Gbps Data Rate on the High-Speed Side and up to 5G bps on the Low-Speed Side
- Differential CML I/Os on Both High-Speed and Low-Speed Sides
- Shared or Independent Reference Clock Per Channel
- Loopback Capability on Both High-Speed and Low-Speed Sides, OBSAI Compliant
- Supports Data Retime Operation
- Supports PRBS 27-1, 223-1 and 231-1 and High-Frequency, Low-Frequency, Mixed-Frequency, and CRPAT Long and Short Pattern Generation and Verification
- Two Power Supplies: 1-V Core, and 1.5-V or 1.8-V I/O
- Transmit De-Emphasis and Receive Adaptive Equalization to Allow Extended Backplane or Cable Reach on Both High-Speed and Low-Speed Sides
- Programmable Transmit Output Swing on Both High-Speed and Low-Speed Sides.
- Minimum Receiver Differential Input Threshold of 100 mVpp
- Loss-of-Signal (LOS) Detection
- Interface to Backplanes, Passive and Active Copper Cables, or SFP/SFP+ Optical Modules
- Hot Plug Protection
- JTAG; IEEE 1149.1 Test Interface
- MDIO; IEEE 802.3 Clause-22 Support
- 65-nm Advanced CMOS Technology
- Industrial Ambient Operating Temperature (–40°C to 85°C) at Full Rate
- Power Consumption: 1.6 W Typical
- Device Package: 13-mm × 13-mm, 144-pin PBGA, 1-mm Ball-Pitch
The TLK10002 device is a dual-channel, multi-rate transceiver intended for use in high-speed bidirectional point-to-point data transmission systems. It has special support for the wireless base station Remote Radio Head (RRH) application, but may also be used in other high-speed applications. It supports all the CPRI and OBSAI rates from 1.2288 Gbps to 9.8304 Gbps.
The TLK10002 performs 1:1, 2:1 and 4:1 serialization of the 8B/10B encoded data streams presented on its low-speed (LS) side data inputs. The serialized 8B/10B encoded data is presented on the high-speed (HS) side outputs. Likewise, the TLK10002 performs 1:1, 1:2 and 1:4 deserialization of 8B/10B encoded data streams presented on its high-speed side data inputs. The deserialized 8B/10B encoded data is presented on the low-speed side outputs. Depending on the serialization or deserialization ratio, the low-speed side data rate can range from 0.5 Gbps to 5 Gbps and the high-speed side data rate can range from 1 Gbps to 10 Gbps. Both low-speed and high-speed side data inputs and outputs are of differential current mode logic (CML) type with integrated termination resistors. In the 1:1 mode, the input can be raw (non-8B/10B encoded) data, allowing for transmission of PRBS data through the device.
The TLK10002 performs data serialization or deserialization and clock extraction as a physical layer interface device. Flexible clocking schemes are provided to support various operations. They include the support for clocking with an externally-jitter-cleaned clock recovered from the high-speed side.
The TLK10002 provides two low-speed side and two high-speed side loopback modes for self-test and system diagnostic purposes.
The TLK10002 has built-in pattern generation and verification to help in system tests. The low speed side supports generation and verification of PRBS 27-1, 223-1, and 231-1 patterns. In addition to those PRBS patterns, the high-speed side supports High, Low, Mixed, and CRPAT long and short pattern generation and verification.
The TLK10002 has an integrated loss-of-signal (LOS) detection function on both high-speed and low-speed sides. LOS is asserted in conditions where the input differential voltage swing is less than the LOS assert threshold. The input differential voltage swing must exceed the de-assert threshold for the LOS condition to be cleared.
Lane alignment for each channel is achieved through a proprietary lane alignment scheme implemented on the low-speed side interface. The interfaced upstream link partner device needs to implement the lane alignment scheme for the correct link operation. Normal link operation resumes only after lane alignment is achieved.
The two TLK10002 channels are fully independent. They can be operated with different reference clocks, at different data rates, and with different serialization or deserialization ratios.
The low-speed side of the TLK10002 is ideal for interfacing with an FPGA or ASIC located on the same local physical system. The high-speed side is ideal for interfacing with remote systems through an optical fiber, an electrical cable, or a backplane interface. The TLK10002 supports operation with SFP and SFP+ optical modules.
Documentación técnica
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Ver todo 5 | Tipo | Título | Fecha | ||
|---|---|---|---|---|
| * | Data sheet | TLK10002 10-Gbps, Dual-Channel, Multi-Rate Transceiver datasheet (Rev. B) | PDF | HTML | 28 jul 2016 |
| Application note | Driving the TLK10002 10Gpbs SERDES with the CDCM6208 Clock Generator | 14 dic 2012 | ||
| Application note | TLK10002 Latency Measurement in Wireless Base Station System | 13 mar 2012 | ||
| User guide | TLK10002 Dual-Channel, 10-Gbps, Multi-Rate Transceiver EVM | 09 may 2011 | ||
| EVM User's guide | TLK10002 Dual-Chnl, 10-Gbps, Multi-Rate Transceiver EVM Graphical User Interface | 07 may 2011 |
Diseño y desarrollo
Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.
Placa de evaluación
TLK10002EVM — Módulo de evaluación TLK10002EVM
Motherboard evaluation module for TLK10002.
Guía del usuario: PDF
Placa de evaluación
TLK10002FPGAEVM — Módulo de evaluación TLK10002FPGAEVM
FPGA daughterboard for the TLK10002 device. The TLK10002 device is a dual-channel, multi-rate transceiver.
Guía del usuario: PDF
Placa de evaluación
TLK10002SMAEVM — Módulo de evaluación TLK10002SMAEVM
SMA breakout daughterboard for TLK10002.
Guía del usuario: PDF
Herramienta de simulación
PSPICE-FOR-TI — PSpice® para herramienta de diseño y simulación de TI
PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Herramienta de simulación
TINA-TI — Programa de simulación analógica basado en SPICE
TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
Guía del usuario: PDF
| Paquete | Pasadores | Descargar |
|---|---|---|
| FCBGA (CTR) | 144 | Ver opciones |
Pedidos y calidad
Información incluida:
- RoHS
- REACH
- Marcado del dispositivo
- Acabado de plomo/material de la bola
- Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
- Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
- Contenido del material
- Resumen de calificaciones
- Monitoreo continuo de confiabilidad
Información incluida:
- Lugar de fabricación
- Lugar de ensamblaje
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