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Circuitos integrados PCIe, SAS y SATA

XIO2001

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Puente de traducción de PCI Express® (PCIe®) a PCI bus

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XIO2001

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Detalles del producto

Type Bridge Protocols PCIe Applications PCIe Number of channels 4 Speed (max) (Gbpp) 2.5 Rating Catalog Operating temperature range (°C) -40 to 85
Type Bridge Protocols PCIe Applications PCIe Number of channels 4 Speed (max) (Gbpp) 2.5 Rating Catalog Operating temperature range (°C) -40 to 85
NFBGA (ZWS) 169 144 mm² (12 mm × 12 mm) NFBGA (ZAJ) 144 49 mm² (7 mm × 7 mm) HTQFP (PNP) 128 256 mm² (16 mm × 16 mm)
  • Full ×1 PCI Express™ Throughput
  • Fully Compliant With PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0
  • Fully Compliant With PCI Express Base Specification, Revision 2.0
  • Fully Compliant With PCI Local Bus Specification, Revision 2.3
  • PCI Express Advanced Error Reporting Capability Including ECRC Support
  • Support for D1, D2, D3hot, and D3cold
  • Active-State Link Power Management Saves Power When Packet Activity on the PCI Express Link is Idle, Using Both L0s and L1 States
  • Wake Event and Beacon Support
  • Error Forwarding Including PCI Express Data Poisoning and PCI Bus Parity Errors
  • Uses 100-MHz Differential PCI Express Common Reference Clock or 125-MHz Single-Ended, Reference Clock
  • Optional Spread Spectrum Reference Clock is Supported
  • Robust Pipeline Architecture to Minimize Transaction Latency
  • Full PCI Local Bus 66-MHz/32-Bit Throughput
  • Support for Six Subordinate PCI Bus Masters with Internal Configurable, 2-Level Prioritization Scheme
  • Internal PCI Arbiter Supporting Up to 6 External PCI Masters
  • Advanced PCI Express Message Signaled Interrupt Generation for Serial IRQ Interrupts
  • External PCI Bus Arbiter Option
  • PCI Bus LOCK Support
  • JTAG/BS for Production Test
  • PCI-Express CLKREQ Support
  • Clock Run and Power Override Support
  • Six Buffered PCI Clock Outputs (25 MHz, 33 MHz, 50 MHz, or 66 MHz)
  • PCI Bus Interface 3.3-V and 5.0-V (25 MHz or 33 MHz only at 5.0 V) Tolerance Options
  • Integrated AUX Power Switch Drains VAUX Power Only When Main Power Is Off
  • Five 3.3-V, Multifunction, General-Purpose I/O Terminals
  • Memory-Mapped EEPROM Serial-Bus Controller Supporting PCI Express Power Budget/Limit Extensions for Add-In Cards
  • Compact Footprint, Lead-Free 144-Ball, ZAJ nFBGA, Lead-Free 169-Ball ZWS nFBGA, and PowerPad™ HTQFP 128-Pin PNP Package
  • Full ×1 PCI Express™ Throughput
  • Fully Compliant With PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0
  • Fully Compliant With PCI Express Base Specification, Revision 2.0
  • Fully Compliant With PCI Local Bus Specification, Revision 2.3
  • PCI Express Advanced Error Reporting Capability Including ECRC Support
  • Support for D1, D2, D3hot, and D3cold
  • Active-State Link Power Management Saves Power When Packet Activity on the PCI Express Link is Idle, Using Both L0s and L1 States
  • Wake Event and Beacon Support
  • Error Forwarding Including PCI Express Data Poisoning and PCI Bus Parity Errors
  • Uses 100-MHz Differential PCI Express Common Reference Clock or 125-MHz Single-Ended, Reference Clock
  • Optional Spread Spectrum Reference Clock is Supported
  • Robust Pipeline Architecture to Minimize Transaction Latency
  • Full PCI Local Bus 66-MHz/32-Bit Throughput
  • Support for Six Subordinate PCI Bus Masters with Internal Configurable, 2-Level Prioritization Scheme
  • Internal PCI Arbiter Supporting Up to 6 External PCI Masters
  • Advanced PCI Express Message Signaled Interrupt Generation for Serial IRQ Interrupts
  • External PCI Bus Arbiter Option
  • PCI Bus LOCK Support
  • JTAG/BS for Production Test
  • PCI-Express CLKREQ Support
  • Clock Run and Power Override Support
  • Six Buffered PCI Clock Outputs (25 MHz, 33 MHz, 50 MHz, or 66 MHz)
  • PCI Bus Interface 3.3-V and 5.0-V (25 MHz or 33 MHz only at 5.0 V) Tolerance Options
  • Integrated AUX Power Switch Drains VAUX Power Only When Main Power Is Off
  • Five 3.3-V, Multifunction, General-Purpose I/O Terminals
  • Memory-Mapped EEPROM Serial-Bus Controller Supporting PCI Express Power Budget/Limit Extensions for Add-In Cards
  • Compact Footprint, Lead-Free 144-Ball, ZAJ nFBGA, Lead-Free 169-Ball ZWS nFBGA, and PowerPad™ HTQFP 128-Pin PNP Package

The XIO2001 is a single-function PCI Express to PCI translation bridge that is fully compliant to the PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0. For downstream traffic, the bridge simultaneously supports up to eight posted and four non-posted transactions. For upstream traffic, up to six posted and four non-posted transactions are simultaneously supported.

The PCI Express interface is fully compliant to the PCI Express Base Specification, Revision 2.0.

The PCI Express interface supports a ×1 link operating at full 250 MB/s packet throughput in each direction simultaneously. Also, the bridge supports the advanced error reporting including extended CRC (ECRC) as defined in the PCI Express Base Specification. Supplemental firmware or software is required to fully use both of these features.

The XIO2001 is a single-function PCI Express to PCI translation bridge that is fully compliant to the PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0. For downstream traffic, the bridge simultaneously supports up to eight posted and four non-posted transactions. For upstream traffic, up to six posted and four non-posted transactions are simultaneously supported.

The PCI Express interface is fully compliant to the PCI Express Base Specification, Revision 2.0.

The PCI Express interface supports a ×1 link operating at full 250 MB/s packet throughput in each direction simultaneously. Also, the bridge supports the advanced error reporting including extended CRC (ECRC) as defined in the PCI Express Base Specification. Supplemental firmware or software is required to fully use both of these features.
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Documentación técnica

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Documentación principal Tipo Título Opciones de formato Descargar la versión más reciente en inglés Fecha
* Hoja de datos XIO2001 PCIe to PCI Bus Translation Bridge datasheet (Rev. J) PDF | HTML 6/12/2020
* Errata XIO2001 Errata (Rev. B) 17/12/2012
Nota sobre la aplicación XIO2001 Implementation Guide. (Rev. D) 19/06/2014
Nota sobre la aplicación XIO2000A to XIO2001 Change Document 28/05/2009

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

XIO2001EVM — Módulo de evaluación XIO2001

The XIO2001EVM evaluation module (EVM) implements a peripheral component interconnect (PCI) express to PCI bridge circuit using the Texas Instruments XIO2001 PCI Express® (PCIe) to PCI bus translation bridge. Designed as a half-width x1 PCIe add-in card, the (...)

Guía del usuario: PDF
Productos y hardware compatibles
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No disponible
Soporte de software

SCPC009 — XIO2001 Performance Tuner

Productos y hardware compatibles
Modelo de simulación

IBIS Model of XIO2001 (ZAJ Package)

SCPM017.ZIP (96 KB) - Modelo IBIS
Productos y hardware compatibles
Modelo de simulación

IBIS Model of XIO2001 (ZGU Package)

SCPM016.ZIP (96 KB) - Modelo IBIS
Productos y hardware compatibles
Modelo de simulación

XIO2001 BSDL Model (Rev. A)

SCPM019 (4 KB) - Modelo BSDL
Productos y hardware compatibles
Encapsulado Pines Símbolos CAD, huellas y modelos 3D
NFBGA (ZWS) 169 Ultra Librarian
NFBGA (ZAJ) 144 Ultra Librarian
HTQFP (PNP) 128 Ultra Librarian
Se aplican los Términos y condiciones estándar de TI para los elementos de evaluación.

Pedidos y calidad

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Soporte y capacitación

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