DS90CR286AT-Q1
- 20 to 66 MHz Shift Clock Support
- 50% Duty Cycle on Receiver Output Clock
- Best–in–Class Setup & Hold Times on
Rx Outputs - Rx Power Consumption < 270 mW (typ)
at 66 MHz Worst Case - Rx Power-down Mode < 200 μW (max)
- ESD Rating: 4 kV (HBM), 1 kV (CDM)
- PLL Requires No External Components
- Compatible with TIA/EIA-644 LVDS Standard
- Low Profile 56-Pin DGG (TSSOP) Package
- Operating Temperature: −40°C to +105°C
- Automotive AEC-Q100 Grade 2 Qualified
The DS90CR286AT-Q1 receiver converts four LVDS (Low Voltage Differential Signaling) data streams back into parallel 28 bits of LVCMOS data. The receiver data outputs strobe on the output clock's rising edge.
The receiver LVDS clock operates at rates from 20 to 66 MHz. The DS90CR286AT-Q1 phase-locks to the input LVDS clock, samples the serial bit streams at the LVDS data lines, and converts them into 28-bit parallel output data. At an incoming clock rate of 66 MHz, each LVDS input line is running at a bit rate of 462 Mbps, resulting in a maximum throughput of 1.848 Gbps.
The DS90CR286AT-Q1 device is enhanced over prior generation receivers due to a wider data valid time on the receiver output. The DS90CR286AT-Q1 is designed for PCB board chip-to-chip OpenLDI-to-RGB bridge conversion. LVDS data transmission over cable interconnect is not recommended for this device.
Users designing a sub-system with a compatible OpenLDI transmitter and DS90CR286AT-Q1 receiver must ensure an acceptable skew margin budget (RSKM). Details regarding RSKM can be found in the Application Information section.
技術資料
| 上位の文書 | タイプ | タイトル | フォーマットオプション | 最新の英語版をダウンロード | 日付 | |
|---|---|---|---|---|---|---|
| * | データシート | DS90CR286AT-Q1 3.3 V Rising Edge Data Strobe LVDS Receiver 28-Bit Channel Link 66 MHz データシート (Rev. A) | PDF | HTML | 2015/12/06 | ||
| アプリケーション・ノート | High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs | 2018/11/09 | ||||
| アプリケーション・ノート | Receiver Skew Margin for Channel Link I and FPD Link I Devices | PDF | HTML | 2016/01/13 |
設計と開発
その他のアイテムや必要なリソースを参照するには、以下のタイトルをクリックして詳細ページをご覧ください。
DS90CR285-86ATQEVM — DS90CR285 および DS90CR286AT-Q1 チャネル リンク I SerDes 評価基板
FLINK3V8BT-85 — FPD-Link ファミリ シリアライザ/ デシリアライザ LVDS 評価キット
FPD-Link evaluation kit contains a Transmitter (Tx) board, a Receiver (Rx) board along with interfacing cables. This kit will demonstrate the chipsets interfacing from test equipment or a graphics controller using Low Voltage Differential Signaling (LVDS) to a receiver board.
The Transmitter board (...)
| パッケージ | ピン数 | CAD シンボル、フットプリント、および 3D モデル |
|---|---|---|
| TSSOP (DGG) | 56 | Ultra Librarian |
購入と品質
推奨製品には、この TI 製品に関連するパラメータ、評価基板、またはリファレンス デザインが存在する可能性があります。