DS92LV18
- 15–66 MHz 18:1/1:18 Serializer/Deserializer (2.376 Gbps Full Duplex Throughput)
- Independent Transmitter and Receiver Operation with Separate Clock, Enable, and Power Down Pins
- Hot Plug Protection (Power Up High Impedance) and Synchronization (Receiver Locks to Random Data)
- Wide ±5% Reference Clock Frequency Tolerance for Easy System Design Using Locally-Generated Clocks
- Line and Local Loopback Modes
- Robust BLVDS Serial Transmission Across Backplanes and Cables for Low EMI
- No External Coding Required
- Internal PLL, No External PLL Components Required
- Single +3.3V Power Supply
- Low Power: 90mA (typ) Transmitter, 100mA (typ) at 66 MHz with PRBS-15 Pattern
- ±100 mV Receiver Input Threshold
- Loss of Lock Detection and Reporting Pin
- Industrial −40 to +85°C Temperature Range
- >2.0kV HBM ESD
- Compact, Standard 80-Pin LQFP Package
All trademarks are the property of their respective owners.
The DS92LV18 Serializer/Deserializer (SERDES) pair transparently translates a 18–bit parallel bus into a BLVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 18-bit, or less, bus over PCB traces and cables by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.
This SERDES pair includes built-in system and device test capability. The line loopback feature enables the user to check the integrity of the serial data transmission paths of the transmitter and receiver while deserializing the serial data to parallel data at the receiver outputs. The local loopback feature enables the user to check the integrity of the transceiver from the local parallel-bus side.
The DS92LV18 incorporates modified BLVDS signaling on the high-speed I/O. BLVDS provides a low power and low noise environment for reliably transferring data over a serial transmission path. The equal and opposite currents through the differential data path control EMI by coupling the resulting fringing fields together.
技術資料
| 上位の文書 | タイプ | タイトル | フォーマットオプション | 最新の英語版をダウンロード | 日付 | |
|---|---|---|---|---|---|---|
| * | データシート | DS92LV18 18-Bit Bus LVDS Serializer/Deserializer - 15-66 MHz データシート (Rev. E) | 2013/04/18 | |||
| アプリケーション・ノート | DS15BA101 & DS15EA101 Enable Long Reach Applications for Embedded Clock SER/DES (Rev. E) | 2013/04/29 | ||||
| アプリケーション・ノート | External Serial Interface Reduces Simultaneous Switching Output Noise in FPGAs (Rev. A) | 2013/04/26 | ||||
| ユーザー・ガイド | 18-Bit SerDes Evaluation Kit User Manual | 2012/01/25 | ||||
| 設計ガイド | 18-bit SerDes Design Guide (DS92LV18, SCAN921821) | 2007/03/29 |
設計と開発
その他のアイテムや必要なリソースを参照するには、以下のタイトルをクリックして詳細ページをご覧ください。
LVDS-18B-EVK — 18 ビット・バス LVDS SERDES 評価ボード 15 ～ 66MHz
The LVDS-18B-EVK is a complete kit for evaluation of National Semiconductor's 18-bit SerDes devices (DS92LV18 and SCAN921821) with low cost twisted pair cables as well as other 100-ohm differential cables.
| パッケージ | ピン数 | CAD シンボル、フットプリント、および 3D モデル |
|---|---|---|
| LQFP (PN) | 80 | Ultra Librarian |
購入と品質
推奨製品には、この TI 製品に関連するパラメータ、評価基板、またはリファレンス デザインが存在する可能性があります。