DS25BR110
- DC - 3.125 Gbps Low Jitter, High Noise Immunity, Low Power Operation
- Four Levels of Receive Equalization Reduce ISI Jitter
- On-Chip 100Ω Input and Output Termination Minimizes Insertion and Return Losses, Reduces Component Count, and Minimizes Board Space
- 7 kV ESD on LVDS I/O Pins Protects Adjoining Components
- Small 3 mm x 3 mm 8-WSON Space Saving Package
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The DS25BR110 is a single channel 3.125 Gbps LVDS buffer optimized for high-speed signal transmission over lossy FR-4 printed circuit board backplanes and balanced metallic cables. A fully differential signal path ensures exceptional signal integrity and noise immunity.
The DS25BR110 features four levels of receive equalization (EQ), making it ideal for use as a receiver device. Other LVDS devices with similar IO characteristics include the following products. The DS25BR120 features four levels of pre-emphasis for use as an optimized driver device, while the DS25BR100 features both pre-emphasis and equalization for use as an optimized repeater device. The DS25BR150 is a buffer/repeater with the lowest power consumption and does not feature transmit pre-emphasis nor receive equalization.
Wide input common mode range allows the receiver to accept signals with LVDS, CML and LVPECL levels; the output levels are LVDS. A very small package footprint requires minimal space on the board while the flow-through pinout allows easy board layout. The differential inputs and outputs are internally terminated with a 100Ω resistor to lower device input and output return losses, reduce component count, and further minimize board space.
기술 자료
| 상위 문서 | 유형 | 직함 | 형식 옵션 | 최신 영어 버전 다운로드 | 날짜 |
|---|---|---|---|---|---|
| * | 데이터 시트 | DS25BR110 3.125 Gbps LVDS Buffer with Receive Equalization datasheet (Rev. E) | 2013. 4. 14 | ||
| 애플리케이션 노트 | Applications of Low-Voltage Differential Signaling (LVDS) in LED Walls | 2020. 10. 29 | |||
| 애플리케이션 노트 | Applications of Low-Voltage Differential Signaling (LVDS) in Ultrasound Scanners | 2019. 6. 29 | |||
| 애플리케이션 노트 | LVDS Repeaters and Crosspoints Extend the Reach of FPD-Link II Interfaces (Rev. A) | 2013. 4. 29 | |||
| 애플리케이션 노트 | AN-1957 LVDS Signal Conditioners Reduce Data-Dependent Jitter (Rev. A) | 2013. 4. 26 | |||
| 사용 설명서 | 3.125 Gbps LVDS Buffers with Pre-emphasis and Equalization User Guide | 2012. 1. 25 | |||
| 애플리케이션 노트 | Extending the Signal Path Over Data Trans Lines Using LVDS Signal Conditioning | 2007. 8. 2 |
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
DS25BR100EVK — 3.125Gbps LVDS 단일 채널 버퍼, 전송 사전 강조 및 수신 이퀄라이제이션 제품군
The DS25BR100EVK is an evaluation kit designed for demonstrating performance of the 3.125 Gbps LVDS Single Channel Buffers with Transmit Pre-Emphasis (PE) and Receive Equalization (EQ) family (DS25BR100, DS25BR110 and DS25BR120). The evaluation kit provides all three devices on a single board and (...)
| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| WSON (NGQ) | 8 | Ultra Librarian |
주문 및 품질
권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.