DS90LV110T
- Low jitter 800 Mbps fully differential data path
- 145 ps (typ) of pk-pk jitter with PRBS = 223−1 data pattern at 800 Mbps
- Single +3.3 V Supply
- Less than 413 mW (typ) total power dissipation
- Balanced output impedance
- Output channel-to-channel skew is 35ps (typ)
- Differential output voltage (VOD) is 320mV (typ) with 100Ω termination load.
- LVDS receiver inputs accept LVPECL signals
- Fast propagation delay of 2.8 ns (typ)
- Receiver input threshold < ±100 mV
- 28 lead TSSOP package
- Conforms to ANSI/TIA/EIA-644 LVDS standard
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DS90LV110 is a 1 to 10 data/clock distributor utilizing LVDS (Low Voltage Differential Signaling) technology for low power, high speed operation. Data paths are fully differential from input to output for low noise generation and low pulse width distortion. The design allows connection of 1 input to all 10 outputs. LVDS I/O enable high speed data transmission for point-to-point interconnects. This device can be used as a high speed differential 1 to 10 signal distribution / fanout replacing multi-drop bus applications for higher speed links with improved signal quality. It can also be used for clock distribution up to 400MHz.
The DS90LV110 accepts LVDS signal levels, LVPECL levels directly or PECL with attenuation networks.
The LVDS outputs can be put into TRI-STATE by use of the enable pin.
For more details, please refer to the Application Information section of this datasheet.
관심 가지실만한 유사 제품
비교 대상 장치와 유사한 기능.
기술 자료
| 상위 문서 | 유형 | 직함 | 형식 옵션 | 최신 영어 버전 다운로드 | 날짜 |
|---|---|---|---|---|---|
| * | 데이터 시트 | DS90LV110T 1 to 10 LVDS Data/Clock Distributor datasheet (Rev. I) | 2013. 4. 16 | ||
| 애플리케이션 노트 | An Overview of LVDS Technology | 1998. 10. 5 |
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
IBIS Model for DS90LV110AT 1 to 10 LVDS Data/Clock Distributor
| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| TSSOP (PW) | 28 | Ultra Librarian |
주문 및 품질
권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.