홈 인터페이스 LVDS, M-LVDS 및 PECL
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인터페이스
LVDS, M-LVDS 및 PECL

EQ50F100

마지막 구매

1Gbps~6.25Gbps 백플레인 이퀄라이저

지금 주문
데이터 시트

EQ50F100

마지막 구매
데이터 시트 지금 주문

제품 상세 정보

Function Equalizer Protocols CML Number of transmitters 1 Number of receivers 1 Supply voltage (V) 1.8 Signaling rate (Mbps) 6250 Input signal CML Output signal CML Rating Catalog Operating temperature range (°C) -40 to 85
Function Equalizer Protocols CML Number of transmitters 1 Number of receivers 1 Supply voltage (V) 1.8 Signaling rate (Mbps) 6250 Input signal CML Output signal CML Rating Catalog Operating temperature range (°C) -40 to 85
WSON (NGG) 6 9 mm² 3 x 3
  • Recovers 6.25 Gbps signals after 30" of FR4
  • Single 1.8V power supply
  • Low power consumption: 85mW
  • Equalize up to 20dB loss at 2.5 GHz
  • 35 ps residual deterministic jitter at 5 Gbps
  • On-chip CML terminations
  • Small 3 mm x 3 mm 6-pin leadless LLP package
  • Recovers 6.25 Gbps signals after 30" of FR4
  • Single 1.8V power supply
  • Low power consumption: 85mW
  • Equalize up to 20dB loss at 2.5 GHz
  • 35 ps residual deterministic jitter at 5 Gbps
  • On-chip CML terminations
  • Small 3 mm x 3 mm 6-pin leadless LLP package

The EQ50F100 is a equalizer designed to compensate transmission medium losses and reduce the medium-induced deterministic jitter. It is optimized for operation from 1Gbps to 6.25Gbps, on printed circuit backplane for up to 30" of FR4 striplines with backplane connectors at both ends. It is code independent, and functioning equally well for short run length, balanced codes such as 8b/10b, commonly used in multiplexed 1.25 Gbps Ethernet Systems.

The equalizer uses differential CML inputs and outputs with feed-through pin-outs, mounted in a 3 mm x 3 mm 6-pin leadless LLP package. It is powered from single 1.8V supply and consumes 85 mW.

The EQ50F100 is a equalizer designed to compensate transmission medium losses and reduce the medium-induced deterministic jitter. It is optimized for operation from 1Gbps to 6.25Gbps, on printed circuit backplane for up to 30" of FR4 striplines with backplane connectors at both ends. It is code independent, and functioning equally well for short run length, balanced codes such as 8b/10b, commonly used in multiplexed 1.25 Gbps Ethernet Systems.

The equalizer uses differential CML inputs and outputs with feed-through pin-outs, mounted in a 3 mm x 3 mm 6-pin leadless LLP package. It is powered from single 1.8V supply and consumes 85 mW.
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유형 직함 날짜
* Data sheet EQ50F100 1Gbps - 6.25 Gbps Backplane Equalizer datasheet (Rev. D) 2005/04/14

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치