LMK1D1204P

활성

핀 제어를 지원하는 4채널 출력 LVDS 1.8V, 2.5V 및 3.3V 버퍼

지금 주문하기

데이터 시트

document-pdfAcrobat LMK1D1204P Pin-Controlled OE Low Additive Jitter LVDS Buffer datasheet (Rev. A) (영어) PDF | HTML

LMK1D1204P

활성

데이터 시트

지금 주문하기

제품 상세 정보

Number of outputs

4

Additive RMS jitter (typ) (fs)

50

Core supply voltage (V)

1.8, 2.5, 3.3

Output supply voltage (V)

1.8, 2.5, 3.3

Output skew (ps)

20

Operating temperature range (°C)

-40 to 105

Rating

Catalog

Output type

LVDS

Input type

HCSL, LP-HCSL, LVCMOS, LVDS, LVPECL

Number of outputs

4

Additive RMS jitter (typ) (fs)

50

Core supply voltage (V)

1.8, 2.5, 3.3

Output supply voltage (V)

1.8, 2.5, 3.3

Output skew (ps)

20

Operating temperature range (°C)

-40 to 105

Rating

Catalog

Output type

LVDS

Input type

HCSL, LP-HCSL, LVCMOS, LVDS, LVPECL

VQFN (RHD)

28

25 mm² (5 mm × 5 mm)

High-performance LVDS clock buffer family with 2 inputs and 4 outputs (2:4)
Output frequency up to 2 GHz
Hardware pins for individual output enable/disable
Supply voltage: 1.8 V / 2.5 V / 3.3 V ± 5%
Low additive jitter: < 60 fs rms maximum in 12 kHz to 20 MHz at 156.25 MHz
- Very low phase noise floor: -164 dBc/Hz (typical)
Very low propagation delay: < 575 ps maximum
Output skew: 20 ps maximum
Fail-safe inputs
Universal inputs accept LVDS, LVPECL, LVCMOS, HCSL and CML
LVDS reference voltage, V AC_REF, available for capacitive-coupled inputs
Industrial temperature range: –40°C to 105°C
Packages available:
- 5-mm × 5-mm, 28-pin VQFN (RHD)

High-performance LVDS clock buffer family with 2 inputs and 4 outputs (2:4)
Output frequency up to 2 GHz
Hardware pins for individual output enable/disable
Supply voltage: 1.8 V / 2.5 V / 3.3 V ± 5%
Low additive jitter: < 60 fs rms maximum in 12 kHz to 20 MHz at 156.25 MHz
- Very low phase noise floor: -164 dBc/Hz (typical)
Very low propagation delay: < 575 ps maximum
Output skew: 20 ps maximum
Fail-safe inputs
Universal inputs accept LVDS, LVPECL, LVCMOS, HCSL and CML
LVDS reference voltage, V AC_REF, available for capacitive-coupled inputs
Industrial temperature range: –40°C to 105°C
Packages available:
- 5-mm × 5-mm, 28-pin VQFN (RHD)

The LMK1D1204P clock buffer distributes one of two selectable clock inputs (IN0 and IN1) to 4 pairs of differential LVDS clock outputs (OUT0 through OUT3) with minimum skew for clock distribution. The inputs can be either LVDS, LVPECL, LVCMOS, HCSL, or CML.

The LMK1D1204P is specifically designed for driving 50-Ω transmission lines. When driving inputs in single-ended mode, apply the appropriate bias voltage to the unused negative input pin. The IN_SEL pin selects the input which is routed to the outputs. The part supports a fail-safe input function. The device further incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.

Each LVDS differential output is enabled by setting the corresponding OEx pin to a logic high "1". If this pin is set to a logic low "0", the output is disabled in a high Z state resulting in reduced power consumption.

The device operates in a 1.8-V, 2.5-V, or 3.3-V supply environment and is characterized from –40°C to 105°C (ambient temperature).

The LMK1D1204P clock buffer distributes one of two selectable clock inputs (IN0 and IN1) to 4 pairs of differential LVDS clock outputs (OUT0 through OUT3) with minimum skew for clock distribution. The inputs can be either LVDS, LVPECL, LVCMOS, HCSL, or CML.

The LMK1D1204P is specifically designed for driving 50-Ω transmission lines. When driving inputs in single-ended mode, apply the appropriate bias voltage to the unused negative input pin. The IN_SEL pin selects the input which is routed to the outputs. The part supports a fail-safe input function. The device further incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.

Each LVDS differential output is enabled by setting the corresponding OEx pin to a logic high "1". If this pin is set to a logic low "0", the output is disabled in a high Z state resulting in reduced power consumption.

The device operates in a 1.8-V, 2.5-V, or 3.3-V supply environment and is characterized from –40°C to 105°C (ambient temperature).

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기타 클록 버퍼 찾기

다운로드 스크립트와 함께 비디오 보기 비디오

관심 가지실만한 유사 제품

open-in-new

대안 비교

비교 대상 장치와 유사한 기능.

LMK1D1204

활성

4채널 출력 LVDS 1.8V 버퍼 Same performance without individual output enable/disable feature

기술 자료

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1개 모두 보기

상위 문서	유형	직함	형식 옵션	최신 영어 버전 다운로드	날짜
*	데이터 시트	LMK1D1204P Pin-Controlled OE Low Additive Jitter LVDS Buffer datasheet (Rev. A)	PDF \| HTML		2023. 6. 14

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

평가 보드

LMK1D1208EVM — LMK1D1208 저지터 2:8 LVDS 팬 아웃 버퍼용 평가 모듈

LMK1D1208은 고성능 저 가산 지터 LVDS 클록 버퍼로, 차동 입력 2개와 LVDS 출력이 8개 있습니다. 이 평가 모듈(EVM)은 LMK1D1208의 전기 성능을 시연할 수 있도록 설계했습니다. 이 EVM은 LMK1Dxxxx 제품군 내에서 다른 28핀 디바이스 평가에도 사용할 수 있습니다. LMK1D1208EVM에는 최고 성능을 위해 50Ω SMA 커넥터와 임피던스 제어 50Ω 마이크로스트립 전송 라인이 내장되어 있습니다.

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