SN65HVD379
- Designed for INTERBUS Applications
- Designed for RS-422 and RS-485 Networks
- Balanced Receiver Thresholds
- 1/2 Unit-Load (up to 64 nodes on the bus)
- Bus-Pin ESD Protection 15 kV HBM
- Bus-Fault Protection of -7 V to 12 V
- Thermal Shutdown Protection
- Power-Up/Down Glitch-free Bus Inputs and Outputs
- High Input Impedance With Low VCC
- Monotonic Outputs During Power Cycling
- 5-V Tolerant Inputs
- APPLICATIONS
- Digital Motor Control
- Utility Meters
- Chassis-to-Chassis Interconnections
- Electronic Security Stations
- Industrial, Process, and Building Automation
- Point-of-Sale (POS) Terminals and Networks
- DTE/DCE Interfaces
The SN65HVD379 is a differential line driver and differential-input line receiver that operates with a 3.3-V power supply. Each driver and receiver has separate input and output pins for full-duplex bus communication designs. They are designed for balanced transmission lines and interoperation with ANSI TIA/EIA-485A, TIA/EIA-422-B, ITU-T v.11, and ISO 8482:1993 standard-compliant devices.
These differential bus drivers and receivers are monolithic, integrated circuits designed for full-duplex bi-directional data communication on multipoint bus-transmission lines at signaling rates(1) up to 25 Mbps. The SN65HVD379 is fully enabled with no external enabling pins.
The 1/2 unit load receiver has a higher receiver input resistance. This results in lower bus leakage currents over the common-mode voltage range, and reduces the total amount of current that an RS-485 driver is forced to source or sink when transmitting.
The balanced differential receiver input threshold makes the SN65HVD379 more compatible with fieldbus requirements that define an external failsafe structure.
(1)The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
기술 자료
| 상위 문서 | 유형 | 직함 | 형식 옵션 | 최신 영어 버전 다운로드 | 날짜 |
|---|---|---|---|---|---|
| * | 데이터 시트 | 3.3 V Full-Duplex RS 485/RS-422 Drivers and Balanced Receivers datasheet (Rev. B) | 2008. 6. 30 |
설계 및 개발
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| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| SOIC (D) | 8 | Ultra Librarian |
주문 및 품질
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