SN65LVDM31
- Designed for Signaling Rates
Up to 150 Mbps - Low-Voltage Differential Signaling With Typical Output Voltage of 700 mV and a 100-
Load - Propagation Delay Time of 2.3 ns, Typical
- Single 3.3-V Supply Operation
- One Driver's Power Dissipation at 75 MHz, 50 mW, Typical
- High-Impedance Outputs When Disabled or With VCC < 1.5 V
- Bus-Pin ESD Protection Exceeds 12 kV
- Low-Voltage CMOS (LVCMOS) Logic Input Levels Are 5-V Tolerant
The signaling rate is the number of voltage transitions that can be made per second.
The SN65LVDM31 incorporates four differential line drivers that implement the electrical characteristics
of low-voltage differential signaling. This product offers a low-power alternative to 5-V
PECL drivers with similar signal levels. Any of the four current-mode drivers will deliver a minimum
differential output voltage magnitude of 540 mV into a 100- load when enabled by either an
active-low or active-high enable input.
The intended application of this device and signaling technique is for both point-to-point and
multiplexed baseband data transmission over controlled impedance media of approximately 100 . The transmission media may be printed-circuit board
traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation
characteristics of the media and the noise coupling to the environment.
The SN65LVDM31 is characterized for operation from -40°C to 85°C.
관심 가지실만한 유사 제품
비교 대상 장치와 유사한 기능.
기술 자료
| 상위 문서 | 유형 | 직함 | 형식 옵션 | 최신 영어 버전 다운로드 | 날짜 |
|---|---|---|---|---|---|
| * | 데이터 시트 | High Speed Differential Line Driver datasheet (Rev. C) | 2002. 2. 6 | ||
| 애플리케이션 노트 | An Introduction to M-LVDS and Clock and Data Distribution Applications (Rev. C) | PDF | HTML | 2023. 6. 22 | ||
| Application brief | How Far, How Fast Can You Operate MLVDS? | 2018. 8. 6 | |||
| 사용 설명서 | Low Voltage Differential Signaling (LVDS) Evaluation Module (EVM) for Quad Drive (Rev. C) | 2010. 2. 16 | |||
| 애플리케이션 노트 | SPI-Based Data Acquisition/Monitor Using the TLC2551 Serial ADC (Rev. A) | 2001. 11. 20 | |||
| 애플리케이션 노트 | An Overview of LVDS Technology | 1998. 10. 5 |
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| SOIC (D) | 16 | Ultra Librarian |
주문 및 품질
권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.