인터페이스 고속 시리얼라이저/디시리얼라이저 FPD-Link 시리얼라이저/디시리얼라이저

SN65LVDS84AQ-Q1

활성

차량용 카탈로그 FlatLink™ 트랜스미터

제품 상세 정보

Applications In-vehicle Infotainment (IVI) Input compatibility LVCMOS Function Serializer Output compatibility LVDS Color depth (bpp) 18 Features Capable to Drive up to 10 meters STP Cable EMI reduction SSC Compatible Rating Automotive Operating temperature range (°C) -40 to 125
Applications In-vehicle Infotainment (IVI) Input compatibility LVCMOS Function Serializer Output compatibility LVDS Color depth (bpp) 18 Features Capable to Drive up to 10 meters STP Cable EMI reduction SSC Compatible Rating Automotive Operating temperature range (°C) -40 to 125
TSSOP (DGG) 48 101.25 mm² (12.5 mm × 8.1 mm)
  • 21:3 Data Channel Compression at up to 196 Mbytes/s Throughput
  • Suited for SVGA, XGA, or SXGA Data Transmission From Controller to Display With Very Low EMI
  • 21 Data Channels Plus Clock In Low-Voltage TTL Inputs and 3 Data Channels Plus Clock Out Low-Voltage Differential Signaling (LVDS) Outputs
  • Operates From a Single 3.3-V Supply and 89 mW (Typ)
  • Packaged in Thin Shrink Small-Outline Package (TSSOP) With 20-Mil Terminal Pitch
  • Consumes Less Than 0.54 mW When Disabled
  • Wide Phase-Lock Input Frequency Range: 31 MHz to 75 MHz
  • No External Components Required for PLL
  • Outputs Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard
  • SSC Tracking Capability of 3% Center Spread at 50-kHz Modulation Frequency
  • Improved Replacement for SN75LVDS84 and NSC DS90CF363A 3-V Device
  • Qualified for Automotive Applications

  • 21:3 Data Channel Compression at up to 196 Mbytes/s Throughput
  • Suited for SVGA, XGA, or SXGA Data Transmission From Controller to Display With Very Low EMI
  • 21 Data Channels Plus Clock In Low-Voltage TTL Inputs and 3 Data Channels Plus Clock Out Low-Voltage Differential Signaling (LVDS) Outputs
  • Operates From a Single 3.3-V Supply and 89 mW (Typ)
  • Packaged in Thin Shrink Small-Outline Package (TSSOP) With 20-Mil Terminal Pitch
  • Consumes Less Than 0.54 mW When Disabled
  • Wide Phase-Lock Input Frequency Range: 31 MHz to 75 MHz
  • No External Components Required for PLL
  • Outputs Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard
  • SSC Tracking Capability of 3% Center Spread at 50-kHz Modulation Frequency
  • Improved Replacement for SN75LVDS84 and NSC DS90CF363A 3-V Device
  • Qualified for Automotive Applications

The SN65LVDS84AQ FlatLink™ transmitter contains three 7-bit parallel-load serial-out shift registers, and four low-voltage differential signaling (LVDS) line drivers in a single integrated circuit. These functions allow 21 bits of single-ended LVTTL data to be synchronously transmitted over 3 balanced-pair conductors for receipt by a compatible receiver, such as the SN75LVDS82 or SN75LVDS86/86A.

When transmitting, data bits D0–D20 are each loaded into registers of the SN65LVDS84AQ upon the falling edge. The internal PLL is frequency-locked to CLKIN and then used to unload the data registers in 7-bit slices. The three serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN.

The SN65LVDS84AQ requires no external components and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The only user intervention is the possible use of the shutdown/clear (SHTDN) active-low input to inhibit the clock and shut off the LVDS output drivers for lower power consumption. A low-level on this signal clears all internal registers to a low level.

The SN65LVDS84AQ is characterized for operation over the full automotive temperature range of –40°C to 125°C.

The SN65LVDS84AQ FlatLink™ transmitter contains three 7-bit parallel-load serial-out shift registers, and four low-voltage differential signaling (LVDS) line drivers in a single integrated circuit. These functions allow 21 bits of single-ended LVTTL data to be synchronously transmitted over 3 balanced-pair conductors for receipt by a compatible receiver, such as the SN75LVDS82 or SN75LVDS86/86A.

When transmitting, data bits D0–D20 are each loaded into registers of the SN65LVDS84AQ upon the falling edge. The internal PLL is frequency-locked to CLKIN and then used to unload the data registers in 7-bit slices. The three serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN.

The SN65LVDS84AQ requires no external components and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The only user intervention is the possible use of the shutdown/clear (SHTDN) active-low input to inhibit the clock and shut off the LVDS output drivers for lower power consumption. A low-level on this signal clears all internal registers to a low level.

The SN65LVDS84AQ is characterized for operation over the full automotive temperature range of –40°C to 125°C.

다운로드 스크립트와 함께 비디오 보기 비디오

기술 자료

검색된 결과가 없습니다. 검색어를 지우고 다시 시도하세요.
1개 모두 보기
상위 문서 유형 직함 형식 옵션 최신 영어 버전 다운로드 날짜
* 데이터 시트 FlatLink (TM) Transmitter datasheet (Rev. A) 2008. 4. 24

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

패키지 CAD 기호, 풋프린트 및 3D 모델
TSSOP (DGG) 48 Ultra Librarian

주문 및 품질

권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.

지원 및 교육

TI 엔지니어의 기술 지원을 받을 수 있는 TI E2E™ 포럼

콘텐츠는 TI 및 커뮤니티 기고자에 의해 "있는 그대로" 제공되며 TI의 사양으로 간주되지 않습니다. 사용 약관을 참조하십시오.

품질, 패키징, TI에서 주문하는 데 대한 질문이 있다면 TI 지원을 방문하세요. ​​​​​​​​​​​​​​

동영상