SN65LVDT250
- Greater Than 2.0 Gbps Operation
- Nonblocking Architecture Allows Each Output to be Connected to Any Input
- Pk.Pk Jitter:
- 60 ps Typical at 2.0 Gbps
- 110 ps Typical at 2.5 Gbps
- Compatible With ANSI TIA/EIA-644-A LVDS Standard
- Available Packaging 38-Pin TSSOP
- 25 mV of Input Voltage Threshold Hysteresis
- Propagation Delay Times: 800 ps Typical
- Inputs Electrically Compatible With LVPECL, CML and LVDS Signal Levels
- Operates From a Single 3.3-V Supply
- Low Power: 110 mA Typical
- Integrated 110-
Line Termination Resistors Available With SN65LVDT250 - APPLICATIONS
- Clock Buffering/Clock Muxing
- Wireless Base Stations
- High-Speed Network Routing
- Telecom/Datacom
The SN65LVDS250 and SN65LVDT250 are 4x4 nonblocking crosspoint switches in a flow-through pin-out allowing for ease in PCB layout. Low-voltage differential signaling (LVDS) is used to achieve a high-speed data throughput while using low power. Each of the output drivers includes a 4:1 multiplexer to allow any input to be routed to any output. Internal signal paths are fully differential to achieve the high signaling speeds while maintaining low signal skews. The SN65LVDT250 incorporates 110- termination resistors for those applications where board space is a premium.
The SN65LVDS250 and SN65LVDT250 are characterized for operation from –40°C to 85°C.
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기술 자료
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1개 모두 보기
| 상위 문서 | 유형 | 직함 | 형식 옵션 | 최신 영어 버전 다운로드 | 날짜 |
|---|---|---|---|---|---|
| * | 데이터 시트 | SN65LVDS250, SN65LVDT250: LVDS 4X4 Crosspoint Switch datasheet (Rev. B) | 2004. 10. 14 |
설계 및 개발
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| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| TSSOP (DBT) | 38 | Ultra Librarian |