SN65LVDT41
- Integrated 110-Ω nominal receiver line termination resistor
- Single 3.3-V power supply (3-V to 3.6-V range)
- Supports signaling rates of at least 250 Mbps
- Flow-through pinout simplifies PCB layout
- LVTTL-compatible logic I/Os
- ESD protection on bus pins exceeds 16 kV
- Meets or exceeds the requirements of ANSI/TIA/EIA-644A standard for LVDS
- 20-pin PW thin shrink small-outline package with 26-mil terminal pitch
The SN65LVDTxx devices are multi-channel LVDS transceivers that operate using LVDS line drivers and receivers. The SN65LVDTxx devices support signaling rates of at least 250 Mbps, and the devices operate from a single supply (typically at 3.3 V) in a 20-pin TSSOP package designed for easy PCB layout.
The SN65LVDT14 and SN65LVDT41 provide general-purpose, asymmetric, bidirectional communication with the added benefit of high noise immunity, low electromagnetic interference (EMI), and increased cable length through the use of LVDS lines. The SN65LVDT14 and SN65LVDT41 are primarily used for SPI over LVDS applications.
The SN65LVDT14 combines one LVDS line driver with four terminated LVDS line receivers in one package. The SN65LVDT14 can be used to extend asymmetric, bidirectional interfaces such as SPI over long distances, and should be located at the SPI slave.
The SN65LVDT41 combines four LVDS line drivers with a single terminated LVDS line receiver in one package. The SN65LVDT41 can be used to extend asymmetric, bidirectional interfaces such as SPI over long distances, and should be located at the SPI master.
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다른 핀 출력을 지원하지만 비교 대상 장치와 동일한 기능.
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기술 자료
| 상위 문서 | 유형 | 직함 | 형식 옵션 | 최신 영어 버전 다운로드 | 날짜 | |
|---|---|---|---|---|---|---|
| * | 데이터 시트 | SN65LVDTxx multi-channel LVDS transceivers SN65LVDT14—One LVDS driver plus four LVDS receivers SN65LVDT41—Four LVDS drivers plus one LVDS receiver datasheet (Rev. C) | PDF | HTML | 2019. 2. 7 | ||
| Application brief | LVDS to Improve EMC in Motor Drives | 2018. 9. 27 | ||||
| Application brief | How Far, How Fast Can You Operate LVDS Drivers and Receivers? | 2018. 8. 3 | ||||
| Application brief | How to Terminate LVDS Connections with DC and AC Coupling | 2018. 5. 16 |
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| TSSOP (PW) | 20 | Ultra Librarian |
주문 및 품질
권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.