SN65MLVD047
- Differential Line Drivers for 30-
Loads and Data Rates(1) Up to 200 Mbps, Clock Frequencies up to 100 MHz - Supports Multipoint Bus Architectures
- Operates from a Single 3.3-V Supply
- Characterized for Operation from -40°C to 85°C
- 16-Pin SOIC (JEDEC MS-012) and 16-Pin TSSOP (JEDEC MS-153) Packaging
- APPLICATIONS
- Clock Distribution
- Backplane or Cabled Multipoint Data Transmission in Telecommunications, Automotive, Industrial, and Other Computer Systems
- Cellular Base Stations
- Central-Office and PBX Switching
- Bridges and Routers
- Low-Power High-Speed Short-Reach Alternative to TIA/EIA-485
(1) The data rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
The SN65MLVD047 is a quadruple line driver. The output current of this device has been increased, in comparison to standard LVDS compliant devices, in order to support doubly terminated transmission lines and heavily loaded backplane bus applications. Backplane applications generally require impedance matching termination resistors at both ends of the bus. The effective impedance of a doubly terminated bus can be as low as 30 . The SN65MLVD047 devices allow for multiple drivers to be present on a single bus. Driver edge rate control is incorporated to support operation. The SN65MLVD047 provides 9-kV ESD protection on all bus pins.
관심 가지실만한 유사 제품
비교 대상 장치와 유사한 기능.
기술 자료
| 상위 문서 | 유형 | 직함 | 형식 옵션 | 최신 영어 버전 다운로드 | 날짜 |
|---|---|---|---|---|---|
| * | 데이터 시트 | Multipoint-LVDS Quad Differential Line Driver datasheet (Rev. A) | 2005. 7. 12 |
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| SOIC (D) | 16 | Ultra Librarian |
| TSSOP (PW) | 16 | Ultra Librarian |
주문 및 품질
권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.