SN65MLVD3
- Low-Voltage Differential 30-
Line Receivers for Signaling Rates(1) up to 250Mbps; Clock Frequencies up to 125MHz - SN65MLVD2 Type-1 Receiver Incorporates 25 mV of Input Threshold Hysteresis
- SN65MLVD3 Type-2 Receiver Provides 100 mV Offset Threshold to Detect Open-Circuit and Idle-Bus Conditions
- Wide Receiver Input Common-Mode Voltage Range, -1 V to 3.4 V, Allows 2 V of Ground Noise
- Improved VIT (35 mV)
- Meets or Exceeds the M-LVDS Standard TIA/EIA-899 for Multipoint Topology
- High Input Impedance with Low Supply Voltage
- Bus-Pin HBM ESD Protection Exceeds 9 kV
- Packaged in 8-Pin SON (DRB) 70% Smaller Than 8-Pin SOIC
- APPLICATIONS
- Parallel Multipoint Data and Clock Transmission via Backplanes and Cables
- Cellular Base Stations
- Central Office Switches
- Network Switches and Routers
(1) The signaling rate of a line is the number of voltage transitions that are made per second, expressed in the units bps (bits per second).
The SN65MLVD2 and SN65MLVD3 are single-channel M-LVDS receivers. These devices are designed in full compliance with the TIA/EIA-899 (M-LVDS) standard, which are optimized to operate at signaling rates up to 250 Mbps. Each receiver channel is controlled by a receive enable (RE). When RE = low, the corresponding channel is enabled; when RE = high, the corresponding channel is disabled.
The M-LVDS standard defines two types of receivers, designated as Type-1 and Type-2. Type-1 receivers (SN65MLVD2) have thresholds centered about zero with 25 mV of hysteresis to prevent output oscillations with loss of input; Type-2 receivers (SN65MLVD3) implement a failsafe by using an offset threshold. Receiver outputs are slew rate controlled to reduce EMI and crosstalk effects associated with large current surges.
The devices are characterized for operation from -40°C to 85°C.
관심 가지실만한 유사 제품
비교 대상 장치와 유사한 기능.
기술 자료
| 상위 문서 | 유형 | 직함 | 형식 옵션 | 최신 영어 버전 다운로드 | 날짜 |
|---|---|---|---|---|---|
| * | 데이터 시트 | Single M-LVDS Receivers datasheet | 2006. 11. 2 | ||
| 애플리케이션 노트 | An Introduction to M-LVDS and Clock and Data Distribution Applications (Rev. C) | PDF | HTML | 2023. 6. 22 | ||
| Application brief | How Far, How Fast Can You Operate MLVDS? | 2018. 8. 6 | |||
| 애플리케이션 노트 | SPI-Based Data Acquisition/Monitor Using the TLC2551 Serial ADC (Rev. A) | 2001. 11. 20 |
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
SN65MLVD2-3EVM — SN65MLVD2-3EVM 평가 모듈
The SN65MLVD2 and SN65MLVD3 are single-channel M-LVDS receivers. These devices are designed in full compliance with the TIA/EIA-899 (M-LVDS) standard, which are optimized to operate at signaling rates up to250 Mbps. Each receiver channel is controlled by a receive enable (/RE). When /RE = low, (...)
| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| VSON (DRB) | 8 | Ultra Librarian |
주문 및 품질
권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.