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SN74AVC2T245-Q1

활성

Automotive 2-bit dual-supply bus transceiver with configurable voltage translation

지금 주문
데이터 시트

SN74AVC2T245-Q1

활성
데이터 시트 지금 주문

제품 상세 정보

Bits (#) 2 Data rate (max) (Mbps) 500 Topology Push-Pull Direction control (typ) Direction-controlled Vin (min) (V) 1.2 Vin (max) (V) 3.6 Vout (min) (V) 1.2 Vout (max) (V) 3.6 Applications GPIO Features Output enable, Partial power down (Ioff), Vcc isolation Technology family AVC Supply current (max) (mA) 0.016 Rating Automotive Operating temperature range (°C) -40 to 125
Bits (#) 2 Data rate (max) (Mbps) 500 Topology Push-Pull Direction control (typ) Direction-controlled Vin (min) (V) 1.2 Vin (max) (V) 3.6 Vout (min) (V) 1.2 Vout (max) (V) 3.6 Applications GPIO Features Output enable, Partial power down (Ioff), Vcc isolation Technology family AVC Supply current (max) (mA) 0.016 Rating Automotive Operating temperature range (°C) -40 to 125
UQFN (RSW) 10 2.52 mm² 1.8 x 1.4
  • Each Channel Has Independent Direction Control
  • Control Inputs VIH/VIL Levels Are Referenced to VCCA Voltage
  • Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.2V to 3.6V Power-Supply Range
  • I/Os Are 4.6V Tolerant
  • Ioff Supports Partial-Power-Down Mode Operation
  • VCC Isolation Feature - If Either VCC Input is at GND, Both Ports are in High-Impedance State
  • Typical Data Rates
    • 500Mbps (1.8V to 3.3V Level-Shifting)
    • 320Mbps (<1.8V to 3.3V Level-Shifting)
    • 320Mbps (Translate to 2.5V or 1.8V)
    • 280Mbps (Translate to 1.5V)
    • 240Mbps (Translate to 1.2V)
  • Latch-Up Performance Exceeds 100mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 5000V Human-Body Model (A114-A)
    • 200V Machine Model (A115-A)
    • 1500V Charged-Device Model (C101)
  • Each Channel Has Independent Direction Control
  • Control Inputs VIH/VIL Levels Are Referenced to VCCA Voltage
  • Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.2V to 3.6V Power-Supply Range
  • I/Os Are 4.6V Tolerant
  • Ioff Supports Partial-Power-Down Mode Operation
  • VCC Isolation Feature - If Either VCC Input is at GND, Both Ports are in High-Impedance State
  • Typical Data Rates
    • 500Mbps (1.8V to 3.3V Level-Shifting)
    • 320Mbps (<1.8V to 3.3V Level-Shifting)
    • 320Mbps (Translate to 2.5V or 1.8V)
    • 280Mbps (Translate to 1.5V)
    • 240Mbps (Translate to 1.2V)
  • Latch-Up Performance Exceeds 100mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 5000V Human-Body Model (A114-A)
    • 200V Machine Model (A115-A)
    • 1500V Charged-Device Model (C101)

This dual-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2V to 3.6V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.2V to 3.6V. This allows for universal low-voltage bidirectional translation between any of the 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V voltage nodes.

The SN74AVC2T245-Q1 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input and the output-enable ( OE) activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode . The device transmits data from the A bus to the B bus when the B-port outputs are activated and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.

The SN74AVC2T245-Q1 control pins (DIR1, DIR2, and OE) are supplied by VCCA.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The VCC isolation feature ensures that if either VCC input is at GND, both ports are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE must be connected to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This dual-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2V to 3.6V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.2V to 3.6V. This allows for universal low-voltage bidirectional translation between any of the 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V voltage nodes.

The SN74AVC2T245-Q1 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input and the output-enable ( OE) activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode . The device transmits data from the A bus to the B bus when the B-port outputs are activated and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.

The SN74AVC2T245-Q1 control pins (DIR1, DIR2, and OE) are supplied by VCCA.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The VCC isolation feature ensures that if either VCC input is at GND, both ports are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE must be connected to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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* Data sheet SN74AVC2T245-Q1 Dual-Bit Dual-Supply Bus Transceiver with Configurable Level-Shifting / Voltage Translation and Tri-State Outputs datasheet PDF | HTML 2025/11/25
Selection guide Logic Guide (Rev. AC) PDF | HTML 2025/11/13
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015/12/02
Application note Voltage Translation Between 3.3-V, 2.5-V, 1.8-V, and 1.5-V Logic Standards (Rev. B) 2015/04/30
User guide LOGIC Pocket Data Book (Rev. B) 2007/01/16
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004/07/08
Application note Selecting the Right Level Translation Solution (Rev. A) 2004/06/22
More literature LCD Module Interface Application Clip 2003/05/09
User guide AVC Advanced Very-Low-Voltage CMOS Logic Data Book, March 2000 (Rev. C) 2002/08/20
More literature Standard Linear & Logic for PCs, Servers & Motherboards 2002/06/13
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 2002/05/22
Application note Dynamic Output Control (DOC) Circuitry Technology And Applications (Rev. B) 1999/07/07
Application note AVC Logic Family Technology and Applications (Rev. A) 1998/08/26

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