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비교 대상 장치보다 업그레이드된 기능을 지원하는 드롭인 대체품
SN74AVC4T245
- Control inputs VIH/VIL levels are referenced to VCCA voltage
- Fully configurable dual-rail design allows each port to operate over the full 1.2V to 3.6V power-supply range
- I/Os Are 4.6V tolerant
- Ioff supports partial power-down-mode operation
- Maximum data rates:
- 380Mbps (1.8V to 3.3V translation)
- 200Mbps (< 1.8V to 3.3V translation)
- 200Mbps (translate to 2.5V or 1.8V)
- 150Mbps (translate to 1.5V)
- 100Mbps (translate to 1.2V)
- Latch-up performance exceeds 100mA per JESD 78, Class II
- ESD protection exceeds JESD 22:
- 8000V Human-Body Model (A114-A)
- 150V Machine Model (A115-A)
- 1000V Charged-Device Model (C101)
This 4-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2V to 3.6V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.2V to 3.6V. The SN74AVC4T245 is optimized to operate with VCCA/VCCB set at 1.4V to 3.6V. It is operational with VCCA/VCCB as low as 1.2V. This allows for universal low-voltage bidirectional translation between any of the 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V voltage nodes.
The SN74AVC4T245 device is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports is always active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.
The SN74AVC4T245 device is designed so that VCCA supplies the control pins (1DIR, 2DIR, 1 OE, and 2 OE).
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
The VCC isolation feature is designed so that if either VCC input is at GND, then both ports are in the high-impedance state.
To put the device in the high-impedance state during power up or power down, tie OE to VCC through a pullup resistor; the current-sinking capability of the driver determines the minimum value of the resistor.
기술 자료
설계 및 개발
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많은 TI 레퍼런스 설계에는 SN74AVC4T245이(가) 포함됩니다.
레퍼런스 디자인 선택 툴을 사용하여 애플리케이션 및 매개 변수에 가장 적합한 설계를 검토하고 식별할 수 있습니다.
패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
---|---|---|
SOIC (D) | 16 | Ultra Librarian |
SOT-23-THN (DYY) | 16 | Ultra Librarian |
TSSOP (PW) | 16 | Ultra Librarian |
TVSOP (DGV) | 16 | Ultra Librarian |
UQFN (RSV) | 16 | Ultra Librarian |
VQFN (RGY) | 16 | Ultra Librarian |
WQFN (BQB) | 16 | Ultra Librarian |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치