홈 로직 및 전압 변환 전압 변환기 및 레벨 시프터 방향 제어 전압 변환기
홈
로직 및 전압 변환
전압 변환기 및 레벨 시프터
방향 제어 전압 변환기

SN74AVC4T245-Q1

활성

구성 가능한 전압 레벨 전환을 지원하는 오토모티브 4비트 듀얼 공급 버스 트랜시버

지금 주문
데이터시트

이 제품의 최신 버전이 있습니다

open-in-new 대안 비교
비교 대상 장치보다 업그레이드된 기능을 지원하는 즉각적 대체품
SN74AXC4T245-Q1 활성 오토모티브 4비트 듀얼 공급 버스 트랜시버 - 구성 가능한 전압 변환 및 3상 출력 포함 A newer version available with wider operating voltage range

SN74AVC4T245-Q1

활성
데이터시트 지금 주문

제품 상세 정보

Technology family AVC Applications JTAG, SPI, UART Bits (#) 4 High input voltage (min) (V) 0.78 High input voltage (max) (V) 3.6 Vout (min) (V) 1.2 Vout (max) (V) 3.6 Data rate (max) (Mbps) 380 IOH (max) (mA) -12 IOL (max) (mA) 12 Supply current (max) (µA) 16 Features Output enable, Overvoltage tolerant inputs, Partial power down (Ioff) Input type Standard CMOS Output type 3-State, Balanced CMOS, Push-Pull Rating Automotive Operating temperature range (°C) -40 to 125
Technology family AVC Applications JTAG, SPI, UART Bits (#) 4 High input voltage (min) (V) 0.78 High input voltage (max) (V) 3.6 Vout (min) (V) 1.2 Vout (max) (V) 3.6 Data rate (max) (Mbps) 380 IOH (max) (mA) -12 IOL (max) (mA) 12 Supply current (max) (µA) 16 Features Output enable, Overvoltage tolerant inputs, Partial power down (Ioff) Input type Standard CMOS Output type 3-State, Balanced CMOS, Push-Pull Rating Automotive Operating temperature range (°C) -40 to 125
TSSOP (PW) 16 32 mm² 5 x 6.4 VQFN (RGY) 16 14 mm² 4 x 3.5
  • Qualified for automotive applications
  • AEC-Q100 qualified with the following results:
    • Device temperature grade 1: –40°C to 125°C ambient operating temperature range
    • Device HBM ESD classification level H3B (JESD 22 A114-A)
    • Device CDM ESD classification level C5 (JESD 22 C101)
  • Function safety capable
  • Control input VIH and VIL levels are referenced to VCCA voltage
  • Fully configurable dual-rail design allows each port to operate over the full 1.2V to 3.6V power-supply range
  • I/Os are 4.6V tolerant
  • Ioff supports partial power-down-mode operation
  • Maximum data rates:
    • 380Mbps (1.8V to 3.3V translation)
    • 200Mbps (<1.8V to 3.3V translation)
    • 200Mbps (translate to 2.5V or 1.8V)
    • 150Mbps (translate to 1.5V)
    • 100Mbps (translate to 1.2V)
  • Latch-up performance exceeds 100mA per JESD 78, Class II
  • Qualified for automotive applications
  • AEC-Q100 qualified with the following results:
    • Device temperature grade 1: –40°C to 125°C ambient operating temperature range
    • Device HBM ESD classification level H3B (JESD 22 A114-A)
    • Device CDM ESD classification level C5 (JESD 22 C101)
  • Function safety capable
  • Control input VIH and VIL levels are referenced to VCCA voltage
  • Fully configurable dual-rail design allows each port to operate over the full 1.2V to 3.6V power-supply range
  • I/Os are 4.6V tolerant
  • Ioff supports partial power-down-mode operation
  • Maximum data rates:
    • 380Mbps (1.8V to 3.3V translation)
    • 200Mbps (<1.8V to 3.3V translation)
    • 200Mbps (translate to 2.5V or 1.8V)
    • 150Mbps (translate to 1.5V)
    • 100Mbps (translate to 1.2V)
  • Latch-up performance exceeds 100mA per JESD 78, Class II

This 4-bit non-inverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2V to 3.6V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.2V to 3.6V. The SN74AVC4T245-Q1 is optimized to operate with VCCA/VCCB set at 1.4V to 3.6V. It is operational with VCCA/VCCB as low as 1.2V. This allows for universal low-voltage bidirectional translation between any of the 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V voltage nodes.

The SN74AVC4T245-Q1 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input and the output-enable ( OE) input activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports is always active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.

The SN74AVC4T245-Q1 is designed so that the control pins (1DIR, 2DIR, 1 OE, and 2 OE) are supplied by VCCA.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The design of the VCC isolation feature places both ports in the high-impedance state if either VCC input is at GND.

To place the device in the high-impedance state during power up or power down, tie OE to VCC through a pullup resistor; the current-sinking capability of the driver determines the minimum value of the resistor.

This 4-bit non-inverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2V to 3.6V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.2V to 3.6V. The SN74AVC4T245-Q1 is optimized to operate with VCCA/VCCB set at 1.4V to 3.6V. It is operational with VCCA/VCCB as low as 1.2V. This allows for universal low-voltage bidirectional translation between any of the 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V voltage nodes.

The SN74AVC4T245-Q1 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input and the output-enable ( OE) input activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports is always active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.

The SN74AVC4T245-Q1 is designed so that the control pins (1DIR, 2DIR, 1 OE, and 2 OE) are supplied by VCCA.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The design of the VCC isolation feature places both ports in the high-impedance state if either VCC input is at GND.

To place the device in the high-impedance state during power up or power down, tie OE to VCC through a pullup resistor; the current-sinking capability of the driver determines the minimum value of the resistor.
open-in-new 기타 방향 제어 전압 변환기 찾기
다운로드 스크립트와 함께 비디오 보기 동영상

기술 문서

star =TI에서 선정한 이 제품의 인기 문서
검색된 결과가 없습니다. 검색어를 지우고 다시 시도하십시오.
모두 보기18
유형 직함 날짜
* Data sheet SN74AVC4T245-Q1 Automotive 4-Bit Dual-Supply Bus Transceiver with Configurable Voltage Translation and 3-State Outputs datasheet (Rev. C) PDF | HTML 2024/02/29
Functional safety information SN74AVC4T245-Q1 Functional Safety FIT Rate, FMD and Pin FMA PDF | HTML 2024/04/18
EVM User's guide AXC Small-Package Evaluation Module User's Guide (Rev. A) PDF | HTML 2021/07/12
Selection guide Voltage Translation Buying Guide (Rev. A) 2021/04/15
Functional safety information SN74AVC4T245-Q1 Functional Safety FIT Rate and Failure Mode Distribution 2019/12/30
Selection guide Logic Guide (Rev. AB) 2017/06/12
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015/12/02
Application note Voltage Translation Between 3.3-V, 2.5-V, 1.8-V, and 1.5-V Logic Standards (Rev. B) 2015/04/30
More literature Automotive Logic Devices Brochure 2014/08/27
User guide LOGIC Pocket Data Book (Rev. B) 2007/01/16
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004/07/08
Application note Selecting the Right Level Translation Solution (Rev. A) 2004/06/22
More literature LCD Module Interface Application Clip 2003/05/09
User guide AVC Advanced Very-Low-Voltage CMOS Logic Data Book, March 2000 (Rev. C) 2002/08/20
More literature Standard Linear & Logic for PCs, Servers & Motherboards 2002/06/13
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 2002/05/22
Application note Dynamic Output Control (DOC) Circuitry Technology And Applications (Rev. B) 1999/07/07
Application note AVC Logic Family Technology and Applications (Rev. A) 1998/08/26

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

평가 보드

14-24-LOGIC-EVM — 14핀~24핀 D, DB, DGV, DW, DYY, NS 및 PW 패키지용 로직 제품 일반 평가 모듈

14-24-LOGIC-EVM 평가 모듈(EVM)은 14핀~24핀 D, DW, DB, NS, PW, DYY 또는 DGV 패키지에 있는 모든 로직 장치를 지원하도록 설계되었습니다.

사용 설명서: PDF | HTML
TI.com에서 구매할 수 없습니다
평가 보드

14-24-NL-LOGIC-EVM — 14핀~24핀 비 리드 패키지용 로직 제품 일반 평가 모듈

14-24-NL-LOGIC-EVM은 14핀~24핀 BQA, BQB, RGY, RSV, RJW 또는 RHL 패키지가 있는 로직 또는 변환 디바이스를 지원하도록 설계된 유연한 평가 모듈(EVM)입니다.

사용 설명서: PDF | HTML
TI.com에서 구매할 수 없습니다
평가 보드

AVCLVCDIRCNTRL-EVM — AVC 및 LVC를 지원하는 방향 제어 양방향 변환 디바이스를 위한 일반 EVM

The generic EVM is designed to support one, two, four and eight channel LVC and AVC direction-controlled translation devices. It also supports the bus hold and automotive -Q1 devices in the same number of channels. The AVC are low voltage translation devices with lower drive strength of 12mA. LVC (...)

사용 설명서: PDF
TI.com에서 구매할 수 없습니다
시뮬레이션 모델

SN74AVC4T245 IBIS Model (Rev. B)

SCEM503B.ZIP (68 KB) - IBIS Model
다운로드
패키지 핀 다운로드
TSSOP (PW) 16 옵션 보기
VQFN (RGY) 16 옵션 보기
TI의 평가 항목에 대한 표준 약관이 적용됩니다.

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

지원 및 교육

TI 엔지니어의 기술 지원을 받을 수 있는 TI E2E™ 포럼

포럼 주제 모두 보기(영문)

콘텐츠는 TI 및 커뮤니티 기고자에 의해 "있는 그대로" 제공되며 TI의 사양으로 간주되지 않습니다. 사용 약관을 참조하십시오.

품질, 패키징, TI에서 주문하는 데 대한 질문이 있다면 TI 지원을 방문하세요. ​​​​​​​​​​​​​​

동영상