TB5D1M
- Functional Replacements for the Agere BDG1A, BPNGA and BDGLA
- Pin-Equivalent to the General-Trade 26LS31 Device
- 2.0 ns Maximum Propagation Delays
- 0.15 ns Output Skew Typical Between ± Pairs
- Capable of Driving 50-
Loads - 5.0-V or 3.3-V Supply Operation
- TB5D1M Includes Surge Protection on
Differential Outputs - TB5D2H No Line Loading When VCC = 0
- Third State Output Capability
- -40°C to 85°C Operating Temp Range
- ESD Protection HBM > 3 kV and CDM > 2 kV
- Available in Gull-Wing SOIC (JEDEC MS-013, DW) and SOIC (D) Packages
- APPLICATIONS
- Digital Data or Clock
Transmission Over
Balanced Transmission Lines
- Digital Data or Clock
Transmission Over
These quad differential drivers are TTL input to pseudo-ECL differential output used for digital data transmission over balanced transmission lines.
The TB5D1M device is a pin and functional replacement for the Agere systems BDG1A and BPNGA quad differential drivers. The TB5D1M has a built-in lightning protection circuit to absorb large transitions on the transmission lines without destroying the device. When the circuit is powered down it loads the transmission line, because of the protection circuit.
The TB5D2H device is a pin and functional replacement for the Agere systems BDG1A and BDGLA quad differential drivers. Upon power down the TB5D2H output circuit appears as an open circuit and does not load the transmission line.
Both drivers feature a 3-state output with a third-state level of less than 0.1 V.
The packaging options available for these quad differential line drivers include a 16-pin SOIC gull-wing (DW) and a 16-pin SOIC (D) package.
Both drivers are characterized for operation from -40°C to 85°C
The logic inputs of this device include internal pull-up
resistors of approximately 40 k that are connected to VCC to ensure a logical high level input if the inputs
are open circuited.
기술 자료
| 상위 문서 | 유형 | 직함 | 형식 옵션 | 최신 영어 버전 다운로드 | 날짜 |
|---|---|---|---|---|---|
| * | 데이터 시트 | TB5D1M, TB5D2H: Quad Differential PECL Drivers datasheet (Rev. C) | 2008. 1. 18 |
설계 및 개발
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| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| SOIC (DW) | 16 | Ultra Librarian |
| SOIC (D) | 16 | Ultra Librarian |