THS4552
- Bandwidth: 150 MHz (G = 1 V/V)
- Differential output slew rate: 220 V/µs
- Gain bandwidth product: 135 MHz
- Negative rail input (NRI), rail-to-rail output (RRO)
- Wide output common-mode control range
- Single-supply operating range: 2.7 V to 5.4 V
- Trimmed-supply current: 1.37 mA per channel at 5 V
- 25°C input offset: ±175 µV (maximum)
- Input offset voltage drift: ±2.0 µV/°C (maximum)
- Differential input voltage noise: 3.3 nV/√ Hz
- HD2: –128 dBc at 2 VPP, 100 kHz
- HD3: –139 dBc at 2 VPP, 100 kHz
- < 50 ns settling time: 4 V Step to 0.01%
- 18-bit settling time: 4 V Step, < 500 ns
The THS4552 fully differential amplifier offers an easy interface from single-ended sources to the differential output required by high-precision analog-to-digital converters (ADCs). Designed for exceptional dc accuracy, low noise, and robust capacitive load driving, this device is well suited for data acquisition systems where high precision is required along with the best signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) through the amplifier and ADC combination.
The THS4552 features the negative rail input required when interfacing a dc-coupled, ground-centered, source signal to a single-supply differential input ADC. Very low dc error and drift terms support the emerging 16- to 20-bit successive-approximation register (SAR) input requirements. A wide-range output common-mode control supports the ADC running from 1.8 V to 5 V supplies with ADC common-mode input requirements from 0.7 V to greater than 3.0 V.
The THS4552 device is characterized for operation over the wide temperature range of –40°C to +125°C, and is available in 16-pin TSSOP and 24-pin VQFN packages.
기술 자료
| 상위 문서 | 유형 | 직함 | 형식 옵션 | 최신 영어 버전 다운로드 | 날짜 | |
|---|---|---|---|---|---|---|
| * | 데이터 시트 | THS4552 Dual-Channel, Low-Noise, Precision, 150-MHz, Fully Differential Amplifier datasheet (Rev. B) | PDF | HTML | 2021. 6. 16 | ||
| Application brief | Why Use an FDA to Drive an ADC? | PDF | HTML | 2026. 1. 8 | |||
| Application brief | Active Filter Design for Differential ADCs (Rev. A) | PDF | HTML | 2025. 10. 8 | |||
| Circuit design | Single-ended input to differential output circuit using a fully-differential amp (Rev. A) | PDF | HTML | 2024. 9. 25 | |||
| 애플리케이션 노트 | Continuous Wave Doppler Signal Chain Designs for TI’s Ultrasound AFE (Rev. A) | PDF | HTML | 2024. 5. 22 | |||
| e북 | Engineer's Guide to High-Speed Amplifiers | PDF | HTML | 2023. 10. 18 | |||
| 애플리케이션 노트 | Attenuator Amplifier Design to Maximize the Input Voltage of Differential ADCs | 2018. 6. 14 | ||||
| e북 | The Signal e-book: A compendium of blog posts on op amp design topics | PDF | HTML | 2017. 3. 28 | |||
| 아날로그 디자인 학술지 | Using single-supply fully diff. amps with neg. input voltages to drive ADCs | 2010. 11. 15 |
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
THS4552PWEVM — THS4552PW 평가 모듈
THS4552RTWEVM — THS4552RTW 평가 모듈
TINA-TI 100kHz MFB filter LG test of Figure 87 THS4551
TINA-TI AC Coupled Single to Differentiate Gain of 2 Figure70 THS4551
TINA-TI ADTL1-4-75 Model Test for Figure 62 THS4551
TINA-TI Attenuator With a Caps Gain of 0.1 Figure81 THS4551
TINA-TI Attenuator With No Caps Gain of 0.1 Figure80 THS4551
TINA-TI Basic Gain of 1 Test Circuit Figure61 THS4551
TINA-TI Differential Audio DAC ZT Design Figure90 THS4551
TINA-TI Differential IO with OPA2192 to FDA to SAR Figure 76 THS4551
TINA-TI Differential Transimpedance LG Sim Figure90 THS4551
TINA-TI Gain of 0.2 100kHz Butterworth MFB Filter Figure87 THS4551
TINA-TI Gain of 5 Single to Different Simplified for Figure72 THS4551
TINA-TI Gain of 5 Single to Different with 10Mhz Bessel Figure93 THS4551
TINA-TI High Gain Single to Different with Feedback Pole and Input C Figure 85
TINA-TI High Gain Single to Different with Feedback Pole Figure 83 THS4551
TINA-TI Single to Differential Attenuator Figure71 THS4551
SBOR022 — TI FDA Calculator
TIDA-010962 — ATE(자동 테스트 장비) 80V 개별 부동 VI 레퍼런스 설계
이 레퍼런스 설계는 4사분면 개별 부동 전압 및 전류(VI) 설계를 나타낸 것입니다. 전압 출력은 ±40V 및 0V~80V 범위를 지원하며, 전류 범위는 500mA, 10mA, 10μA의 세 가지입니다. 이 설계는 아날로그 피드백 루프를 지원하며 FV(강제 전압), FI(강제 전류), 버퍼, 갱 모드에서 작동합니다. 이 레퍼런스 설계는 20비트 강제 DAC(디지털-아날로그 컨버터), 18비트, 2채널 ADC(아날로그-디지털 컨버터) 및 정밀 신호 체인을 사용해 보정 후 제어 측정에 0.01%의 정확도를 달성합니다.
| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| WQFN (RTW) | 24 | Ultra Librarian |
| TSSOP (PW) | 16 | Ultra Librarian |