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SN74ALVC125

ACTIVE

4-ch, 1.65-V to 3.6-V buffers with 3-state outputs

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Data sheet

SN74ALVC125

ACTIVE
Data sheet Order now

Product details

Technology family ALVC Number of channels 4 IOL (max) (mA) 24 Supply current (max) (µA) 10 IOH (max) (mA) -24 Input type Standard CMOS Output type 3-State Features Balanced outputs, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 85
Technology family ALVC Number of channels 4 IOL (max) (mA) 24 Supply current (max) (µA) 10 IOH (max) (mA) -24 Input type Standard CMOS Output type 3-State Features Balanced outputs, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 85
TSSOP (PW) 14 32 mm² (5 mm × 6.4 mm) SOIC (D) 14 51.9 mm² (8.65 mm × 6 mm) TVSOP (DGV) 14 23.04 mm² (3.6 mm × 6.4 mm) SOP (NS) 14 79.56 mm² (10.2 mm × 7.8 mm)
  • Operates From 1.65 V to 3.6 V
  • Max tpd of 2.8 ns at 3.3 V
  • ±24-mA Output Drive at 3.3 V
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Operates From 1.65 V to 3.6 V
  • Max tpd of 2.8 ns at 3.3 V
  • ±24-mA Output Drive at 3.3 V
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

This quadruple bus buffer gate is designed for 1.65-V to 3.6-V VCC operation.

The SN74ALVC125 features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE)\ input is high.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This quadruple bus buffer gate is designed for 1.65-V to 3.6-V VCC operation.

The SN74ALVC125 features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE)\ input is high.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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* Data sheet SN74ALVC125 datasheet (Rev. H) Sep 17, 2004

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

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Simulation model

HSPICE MODEL OF SN74ALVC125

SCEJ216.ZIP (97 KB) - HSpice model
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Simulation model

SN74ALVC125 Behavioral SPICE Model

SCEM765.ZIP (7 KB) - PSpice model
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Simulation model

SN74ALVC125 IBIS Model

SCEM243.ZIP (45 KB) - IBIS model
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Reference design

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Supported products & hardware
Package Pins CAD symbols, footprints & 3D models
TSSOP (PW) 14 Ultra Librarian
SOIC (D) 14 Ultra Librarian
TVSOP (DGV) 14 Ultra Librarian
SOP (NS) 14 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

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